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l q QT1100A-isg a dvanced i nformation 10 k ey qt ouch ? s ensor ic applications ? appliance controls ? pointing devices ? gaming machines ? pc peripherals ? television controls ? instrument panels QT1100A charge-transfer (?qt?) qtouch ics are self-contained digital controllers capable of detecting near-proximity or touch o n up to 10 electrodes. this device allows each electrode to project an independent sense field through glass or plastic. these devices require only a few inexpensive passive components per sensing channel. the devices are designed specifically for human interfaces, such as control panels, appliances, gaming devices, lighting controls, or anywhere a mechanical switch may be found. each key channel operates independently, and can be tuned to a unique sensitivity level by simply changing setup values in an eeprom or via a serial interface. an external eeprom can store the setups permanently for standalone applications, for example when using the scanport, or, the eeprom can be omitted if the serial port is used to send setup information after each power-up . included is patent pending aks? adjacent key suppression which suppresses touch from weakly responding keys and allows only a dominant key to detect, to solve the problem of large fingers on tightly spaced keys. modulated burst technology provides super ior noise rejection. ?fast-di? operation works to further suppress false activations due to noise. these devices also have a sync pin to suppress some forms of external interference. a sleep mode is also available for very low power standby operation. the QT1100A is designed specifically to assist in creating fmea compliant designs, allowing it to be used in applications such as appliance controls. using the charge transfer principle, these devices deliver a level of performance which is clearly superior to older technologi es yet extremely cost-effective. l q 1 copyright ? 2003-2005 qrg ltd QT1100A-isg r3.02/1105 z 10 independent touch sensing fields z 100% autocal for life - no adjustments required z spi and uart serial interfaces z scanport output - simulates a membrane keypad z simple external per channel passive circuit z user-defined setups of operating parameters z 3.3v~5.0v single supply operation z aks? adjacent key suppression for tight key layouts z sleep mode for low power operation z spread spectrum modulated bursts - superior noise rejection z sync pin for superior mains frequency noise rejection z fmea compliant design features - self detects faults z lower per key cost than many mechanical switches z lead-free package yes QT1100A-isg -40oc to +85oc lead-free ssop-48 t a available options actual size
19 3.5.2 reference for key ?k? - 0x4k .................. 19 3.5.1 signal for 1 key - 0x2k ..................... 19 3.5 status commands ....................... 19 3.4.7 cal key ?k? - 0x1k ....................... 18 3.4.6 sleep - 0x05 ......................... 18 3.4.5 force reset - 0x04 ...................... 18 3.4.4 enter cal mode - 0x03 ..................... 18 3.4.3 enter run mode - 0x02 .................... 17 3.4.2 enter setups load mode - 0x01 ................. 17 3.4.1 null command - 0x00 ..................... 17 3.4 control commands ....................... 16 3.3 communication error handling ................. 16 3.2.3 crdy operation in spi mode .................. 16 3.2.2 sleep/wake operation in spi mode ............... 16 3.2.1 multi-drop spi capability .................... 16 3.2 spi operation .......................... 15 3.1.3 crdy operation in uart mode ................ 15 3.1.2 sleep/wake operation in uart mode .............. 15 3.1.1 tx pin ............................ 15 3.1 uart interface ......................... 15 3 serial operation ......................... 14 2.16 error detection and reporting ................. 14 2.15 start-up sequencing ...................... 14 2.14 scanport interface ....................... 14 2.13 eeprom functionality ..................... 14 2.12 standalone operation, no eeprom .............. 13 2.11 operating parameter setups .................. 13 2.10 start-up time ......................... 13 2.9.2 external fields ........................ 13 2.9.1 led traces and other switching signals ............. 13 2.9 noise issues .......................... 13 2.8 esd protection ......................... 12 2.7 pcb layout and construction .................. 12 2.6 power supply .......................... 12 2.5 sensitivity balance ....................... 12 2.4 sensitivity ............................ 12 2.3 cs sample capacitors ...................... 12 2.2 spread spectrum modulation .................. 12 2.1 oscillator ............................ 12 2 device control & wiring .................... 11 figure 1.3 scanport only connection diagram+ ........... 10 figure 1.2 uart / scanport connection diagram .......... 9 figure 1.1 spi connection diagram ................. 8 table 1.5 pin descriptions ...................... 7 table 1.4 spi pinlist ......................... 6 table 1.3 standalone pinlist ..................... 5 table 1.2 standalone pinlist ..................... 4 table 1.1 scanport / uart pinlist .................. 3 1 overview .............................. 41 6 appendix a - 8-bit crc c algorithm ............. 40 5.10 marking ............................ 40 5.9 mechanical ........................... 40 5.8 current vs vdd ......................... 39 5.7 QT1100A timing parameters - with fosc = 12mhz ....... 38 5.6 spi timing diagram ...................... 37 5.5 burst / sync timing ....................... 36 5.4 dc specifications ........................ 36 5.3 ac specifications ........................ 36 5.2 recommended operating conditions .............. 36 5.1 absolute maximum specifications ................ 36 5 - specifications .......................... 32 4.17 timing tables ......................... 31 table 4-1 serial / eeprom setups block .............. 30 4.16 hcrc - host crc ....................... 29 4.15 br - baud rate control bits .................. 29 4.14 bs - burst spacing control bits ................ 29 4.13 lbll - lower burst length limit ................ 28 4.12 se, sync control bits ..................... 28 4.11 phys - positive hysteresis bits ................ 28 4.10 pthr - positive threshold bits ................. 27 4.9 ndil, fdil - detect integrator bits ................ 27 4.8 k2l / ledp / keyo control bits ................. 27 4.7 ek - error key control bits ................... 26 4.6 aks - adjacent key suppression bits .............. 26 4.5 prd - positive recal delay bits ................. 26 4.4 nrd - negative recal delay bits ................ 25 4.3 ndcr / pdcr - drift comp bits ................. 25 4.2 nhys - negative hysteresis bits ................ 25 4.1 nthr - negative threshold bits ................. 25 4 setup block functions ..................... 24 table 3-2 status commands .................... 23 table 3-1 control commands .................... 22 figure 3-1 suggested serial flow .................. 21 3.6 command sequencing ..................... 21 3.5.14 quick report first key - 0xc9 ................. 21 3.5.13 dump setups block - 0xc8 .................. 21 3.5.12 return last command - 0xc7 ................. 21 3.5.11 internal code - 0xc6 ..................... 21 3.5.10 error flags for group - 0xc5 ................. 20 3.5.9 ram crc - 0xc4 ....................... 20 3.5.8 eeprom crc - 0xc3 ..................... 20 3.5.7 device status - 0xc2 ..................... 20 3.5.6 report all keys - 0xc1 ..................... 20 3.5.5 report 1st key - 0xc0 ..................... 19 3.5.4 status for key ?k? - 0x8k .................... 19 3.5.3 detect integrator for key ?k? - 0x6k ................ l q 2 copyright ? 2003-2005 qrg ltd QT1100A-isg r3.02/1105 contents
1 overview the QT1100A is a 10 touch-key sensor ic based on quantum?s patented charge-transfer principles for robust operation and ease of design. this device has many advanced features which provide for reliable, trouble-free operation over the life of the product. it can operate in either a standalone mode or under host control via a serial interface. output options include uart and spi serial types and parallel scanport. in any interface mode, a low-cost optional eeprom can be used to determine the device configuration using a stored setup block . fmea self-testing: this part has been designed specifically for demanding appliance applications requiring fmea certification. the part has many advanced features that check for and report failures, to allow the designer to create a safer product. it also features two robust serial interfaces with sophisticated crc error checking to permit validation of commands and responses in real time. burst mode: the device operates in ?burst mode?. each key is acquired using a burst of charge-transfer sensing pulses whose count can vary tremendously depending on the value of the reference capacitor cs and the load capacitance cx. the keys (also called ?channels?) are acquired time sequentially within fixed timeslots whose width can be controlled by user-defined setups. self-calibration: on power-up, all keys are self-calibrated within a few hundred milliseconds to provide reliable operation under almost any set of conditions. auto-recalibration : the device can time out and recalibrate each key independently after a fixed interval of continuous detection, so that the keys can never become ?stuck on? due to foreign objects or sudden influences. after recalibration the key will continue to function normally. drift compensation operates to correct the reference level of each key slowly but automatically over time, to suppress false detections caused by changes such as temperature, humidity, dirt and other environmental effects. spread spectrum operation: the bursts operate over a spread of frequencies, so that external fields will have minimal effect on key operation and emissions are very weak. spread-spectrum operation works with the ?detect integrator? (di) mechanism to dramatically reduce the probability of false detection due to noise. detection confirmation occurs by means of a ?detect integrator? mechanism that requires multiple confirmations of detection over a number of key bursts. the bursts operate at alternating frequencies, so that external fields will have a minimal effect on key operation. this spread-spectrum mode of operation also reduces rf noise emissions. the device also features the ability to acquire and lock onto touch signals very rapidly, greatly improv ing response time through the use of the ?fast detect integration? or ?fast-di? feature. sync mode: the QT1100A features a sync mode to allow the device to slave to an external signal source, such as a mains signal (50/60hz), to limit interference effects. this is performed using a special sync pin. low power sleep mode: the device features a low power sleep mode for microamp levels of current drain when not in use. the part can be put into sleep for a certain percentage of the time, so that it can still respond to touch but with lower levels of current drain. aks? adjacent key suppression works to prevent multiple keys responding to a single touch, a common complaint of capacitive touch panels. this system operates by comparing signal strengths from keys within a defined group to suppress touch detections from those with a weaker signal change than the dominant key. the QT1100A allows any aks grouping of two or more keys, under user control. unique to this device is the ability for the designer to treat each key as an individual sensor for configuration purposes. each key can be programmed separately for sensitivity, drift compensation, recalibration timeouts, adjacent key suppression, and the like. the device is designed to support fmea-qualified applications using a variety of checks and redundancies. among other checks the component uses crc codes in all critical communication transfers, and can also output error condition codes via redundant signaling paths. l q 3 copyright ? 2003-2005 qrg ltd QT1100A-isg r3.02/1105
table 1.1 scanport / uart pinlist with or without eeprom; either uart or scanport or both may be used vss or open to cs2 sense pin i/o sns2k 48 open to cs2 + key sense pin i/o sns2 47 vss or open to cs1 sense pin i/o sns1k 46 open to cs1 + key sense pin i/o sns1 45 vss or open to cs0 sense pin i/o sns0k 44 open to cs0 + key sense pin i/o sns0 43 - - unused - n/c 42 - - unused - n/c 41 - - unused - n/c 40 - - unused - n/c 39 open - resonator o osc2 38 - 12mhz - can also be ext clock in resonator i osc1 37 - +3.3 ~ +5v power pwr vdd 36 vdd active low reset input i rst 35 open - led & status o led/stat 34 20k ~ 220k to vdd always use pull-up r sync in i/o sync 33 - to vss comms select i cmode 32 vss see table 2.1 scanport in i scani_0 31 vss see table 2.1 scanport in i scani_1 30 vss see table 2.1 scanport in i scani_2 29 open see table 2.1 scanport out o scano_3 28 open see table 2.1 scanport out o scano_2 27 open see table 2.1 scanport out o scano_1 26 open see table 2.1 scanport out o scano_0 25 open eeprom chip select; use pull-down-r eeprom o csee 24 10k ~ 220k to vdd 1 = comms ready; use pull-up-r handshake i/o, od crdy 23 vdd serial in / wake from sleep uart, wakeup i rx/wake 22 vss serial to host; if used, use pull-up-r uart od tx 21 vdd data in from eeprom eeprom i diee 20 open data out to eeprom eeprom o doee 19 open clock to eeprom eeprom o ckee 18 - 0v ground pwr vss 17 vss or open to cs9 + key sense pin i/o sns9k 16 open to cs9 sense pin i/o sns9 15 vss or open to cs8 + key sense pin i/o sns8k 14 open to cs8 sense pin i/o sns8 13 - - unused - n/c 12 - - unused - n/c 11 vss or open to cs7 + key sense pin i/o sns7k 10 open to cs7 sense pin i/o sns7 9 vss or open to cs6 + key sense pin i/o sns6k 8 open to cs6 sense pin i/o sns6 7 vss or open to cs5 + key sense pin i/o sns5k 6 open to cs5 sense pin i/o sns5 5 vss or open to cs4 + key sense pin i/o sns4k 4 open to cs4 sense pin i/o sns4 3 vss or open to cs3 + key sense pin i/o sns3k 2 open to cs3 sense pin i/o sns3 1 if unused notes function type name pin i cmos input i/o cmos i/o o cmos output (push-pull) od cmos open drain i/o pwr power / ground l q 4 copyright ? 2003-2005 qrg ltd QT1100A-isg r3.02/1105
table 1.2 standalone pinlist scanport, with eeprom; no serial interface vss or open to cs2 sense pin i/o sns2k 48 open to cs2 + key sense pin i/o sns2 47 vss or open to cs1 sense pin i/o sns1k 46 open to cs1 + key sense pin i/o sns1 45 vss or open to cs0 sense pin i/o sns0k 44 open to cs0 + key sense pin i/o sns0 43 - - unused - n/c 42 - - unused - n/c 41 - - unused - n/c 40 - - unused - n/c 39 open - resonator o osc2 38 - 12mhz - can also be ext clock in resonator i osc1 37 - +3.3 ~ +5v power pwr vdd 36 vdd active low reset input i rst 35 open - led & status o led/stat 34 20k ~ 220k to vdd always use pull-up r sync in i/o sync 33 - to vss comms select i cmode 32 vss see table 2.1 scanport in i scani_0 31 vss see table 2.1 scanport in i scani_1 30 vss see table 2.1 scanport in i scani_2 29 open see table 2.1 scanport out o scano_3 28 open see table 2.1 scanport out o scano_2 27 open see table 2.1 scanport out o scano_1 26 open see table 2.1 scanport out o scano_0 25 - eeprom chip select eeprom o csee 24 - leave open handshake i/o, od crdy 23 - to vdd uart, wakeup i rx/wake 22 - to vss uart od tx 21 - data in from eeprom eeprom i diee 20 - data out to eeprom eeprom o doee 19 - clock to eeprom eeprom o ckee 18 - 0v ground pwr vss 17 vss or open to cs9 + key sense pin i/o sns9k 16 open to cs9 sense pin i/o sns9 15 vss or open to cs8 + key sense pin i/o sns8k 14 open to cs8 sense pin i/o sns8 13 - - unused - n/c 12 - - unused - n/c 11 vss or open to cs7 + key sense pin i/o sns7k 10 open to cs7 sense pin i/o sns7 9 vss or open to cs6 + key sense pin i/o sns6k 8 open to cs6 sense pin i/o sns6 7 vss or open to cs5 + key sense pin i/o sns5k 6 open to cs5 sense pin i/o sns5 5 vss or open to cs4 + key sense pin i/o sns4k 4 open to cs4 sense pin i/o sns4 3 vss or open to cs3 + key sense pin i/o sns3k 2 open to cs3 sense pin i/o sns3 1 if unused notes function type name pin i cmos input i/o cmos i/o o cmos output (push-pull) od cmos open drain i/o pwr power / ground l q 5 copyright ? 2003-2005 qrg ltd QT1100A-isg r3.02/1105
table 1.3 standalone pinlist scanport, without eeprom; no serial interface vss or open to cs2 sense pin i/o sns2k 48 open to cs2 + key sense pin i/o sns2 47 vss or open to cs1 sense pin i/o sns1k 46 open to cs1 + key sense pin i/o sns1 45 vss or open to cs0 sense pin i/o sns0k 44 open to cs0 + key sense pin i/o sns0 43 - - unused - n/c 42 - - unused - n/c 41 - - unused - n/c 40 - - unused - n/c 39 open - resonator o osc2 38 - 12mhz - can also be ext clock in resonator i osc1 37 - +3.3 ~ +5v power pwr vdd 36 vdd active low reset input i rst 35 open - led & status o led/stat 34 20k ~ 220k to vdd always use pull-up r sync in i/o sync 33 - to vss comms select i cmode 32 vss see table 2.1 scanport in i scani_0 31 vss see table 2.1 scanport in i scani_1 30 vss see table 2.1 scanport in i scani_2 29 open see table 2.1 scanport out o scano_3 28 open see table 2.1 scanport out o scano_2 27 open see table 2.1 scanport out o scano_1 26 open see table 2.1 scanport out o scano_0 25 - open eeprom o csee 24 - leave open handshake i/o, od crdy 23 - to vdd uart, wakeup i rx/wake 22 - to vss uart od tx 21 - eeprom i diee 20 - connect doee, diee together eeprom o doee 19 - open eeprom o ckee 18 - 0v ground pwr vss 17 vss or open to cs9 + key sense pin i/o sns9k 16 open to cs9 sense pin i/o sns9 15 vss or open to cs8 + key sense pin i/o sns8k 14 open to cs8 sense pin i/o sns8 13 - - unused - n/c 12 - - unused - n/c 11 vss or open to cs7 + key sense pin i/o sns7k 10 open to cs7 sense pin i/o sns7 9 vss or open to cs6 + key sense pin i/o sns6k 8 open to cs6 sense pin i/o sns6 7 vss or open to cs5 + key sense pin i/o sns5k 6 open to cs5 sense pin i/o sns5 5 vss or open to cs4 + key sense pin i/o sns4k 4 open to cs4 sense pin i/o sns4 3 vss or open to cs3 + key sense pin i/o sns3k 2 open to cs3 sense pin i/o sns3 1 if unused notes function type name pin i cmos input i/o cmos i/o o cmos output (push-pull) od cmos open drain i/o pwr power / ground l q 6 copyright ? 2003-2005 qrg ltd QT1100A-isg r3.02/1105
table 1.4 spi pinlist with or without eeprom vss or open to cs2 sense pin i/o sns2k 48 open to cs2 + key sense pin i/o sns2 47 vss or open to cs1 sense pin i/o sns1k 46 open to cs1 + key sense pin i/o sns1 45 vss or open to cs0 sense pin i/o sns0k 44 open to cs0 + key sense pin i/o sns0 43 - - unused - n/c 42 - - unused - n/c 41 - - unused - n/c 40 - - unused - n/c 39 open - resonator o osc2 38 - 12mhz - can also be ext clock in resonator i osc1 37 - +3.3 ~ +5v power pwr vdd 36 vdd active low reset input i rst 35 open - led & status o led/stat 34 20k ~ 220k to vdd always use pull-up r sync in i/o sync 33 - to vdd comms select i cmode 32 - to vss unused i n/c 31 - to vss unused i n/c 30 - from host spi slave select i /ss 29 - from host spi data i di 28 - to host; use pull-up r spi data i/o do 27 - from host spi clock i clk 26 vss - unused i n/c 25 open eeprom chip select; use pull-down r eeprom o csee 24 - 1 = comms ready; use pull-up r spi handshake od crdy 23 vdd wake from sleep wake i wake 22 - to vss unused - n/c 21 vdd data in from eeprom eeprom i diee 20 open data out to eeprom eeprom o doee 19 open clock to eeprom eeprom o ckee 18 - 0v ground pwr vss 17 vss or open to cs9 + key sense pin i/o sns9k 16 open to cs9 sense pin i/o sns9 15 vss or open to cs8 + key sense pin i/o sns8k 14 open to cs8 sense pin i/o sns8 13 - - unused - n/c 12 - - unused - n/c 11 vss or open to cs7 + key sense pin i/o sns7k 10 open to cs7 sense pin i/o sns7 9 vss or open to cs6 + key sense pin i/o sns6k 8 open to cs6 sense pin i/o sns6 7 vss or open to cs5 + key sense pin i/o sns5k 6 open to cs5 sense pin i/o sns5 5 vss or open to cs4 + key sense pin i/o sns4k 4 open to cs4 sense pin i/o sns4 3 vss or open to cs3 + key sense pin i/o sns3k 2 open to cs3 sense pin i/o sns3 1 if unused notes function type name pin i cmos input i/o cmos i/o o cmos output (push-pull) od cmos open drain i/o pwr power / ground l q 7 copyright ? 2003-2005 qrg ltd QT1100A-isg r3.02/1105
table 1.5 pin descriptions connect to 12mhz resonator; leave open if external clock is used osc2 connect to 12mhz resonator; can also be an external clock input osc1 reset input, low resets device. normally this pin can be tied to vdd, or driven from a host controller. /rst led & status output pin. this pin can sink 1ma to drive a status led, or be used by a host controller to determine device error condition or status . led/stat sync input to synchronize acquisitions to an external source or another qt chip. always use a pull-up resistor on this pin. sync communications mode select pin. for uart or scanport operation, connect to vss. for spi mode, connect to vdd. cmode input scan lines scani_x output scan lines scano_x spi slave select from host /ss spi data in from host di spi data output to host. always use a pull -up resistor on this pin. do spi clock input from host clk chip select drive to serial eeprom. always use a pull-down resistor on this pin. csee serial interface handshake pin; bidirectional in uart mode, output only in spi mode. always use a pull-up resistor on this pin. crdy receive pin in uart mode; alternately or in addition, wake from sleep rx/wake serial port pin for uart tx input data line, from serial eeprom diee output data line, to serial eeprom doee clock line output, to drive serial eeprom ckee sense pin, to cs and to key electrode snsnk sense pin, to cs reference capacitor snsn description pin l q 8 copyright ? 2003-2005 qrg ltd QT1100A-isg r3.02/1105
figure 1.1 spi connection diagram do di vdd clk /ss spi to/from host vdd key9 key7 key4 22nf 22nf 22nf regulator QT1100A-as wake crdy vdd key2 key8 key6 key5 key3 vunreg *10uf 10k 2.2k 2.2k 2.2k 2.2k 2.2k 2.2k 22nf 2.2k *4.7uf 4.7k vdd 2.2k 2.2k sync vdd 22k vdd 4.7k 4.7k key1 key0 4.7k vdd 22nf 22nf 22nf 2.2k 22k 4.7k 22nf 93lc46a 4.7k 4.7k 4.7k vi vo g *100nf reset 12mhz 3-term resonator 22nf 22nf 22k 4.7k 4.7k 4.7k 2 clk 1 cs 3 din 4 dout 7 nc 6 nc 5 vss 8 vdd vdd *one bypass capacitor to be tightly coupled to pins 36 and 17. follow regulator manufacturer's recommendations for input and output capacitors. note 1: eeprom is optional when using spi interface. note 2: see table 1.4 for unused pin connections. l q 9 copyright ? 2003-2005 qrg ltd QT1100A-isg r3.02/1105
figure 1.2 uart / scanport connection diagram shown with optional eeprom tx vdd vdd key9 key7 key4 22nf 22nf 22nf regulator QT1100A-as rx/wake crdy scano_0 scano_2 scano_3 scani_0 vdd key2 key8 key6 key5 key3 vunreg *10uf 2.2k 2.2k 2.2k 2.2k 2.2k 2.2k 22nf 2.2k *4.7uf 4.7k 2.2k 2.2k scani_2 scano_1 sync vdd scani_1 vdd 4.7k 4.7k key1 key0 4.7k vdd 22nf 22nf 22nf 2.2k 22k 10k 4.7k 22nf 22k 10k 93lc46a 4.7k 4.7k 4.7k vi vo g *100nf reset 22k 12mhz 3-pin resonator 22nf 22nf 4.7k 4.7k 4.7k 2 clk 1 cs 3 din 4 dout 7 nc 6 nc 5 vss 8 vdd uart to/from host vdd scanport to/from host *one bypass capacitor to be tightly coupled to pins 36 and 17. follow regulator manufacturer's recommendations for input and output capacitors. note 1: eeprom is optional when using uart interface in this drawing. note 2: uart interface is not normally used when using scanport interface and vice versa. note 3: see table 1.1 for unused pin connections l q 10 copyright ? 2003-2005 qrg ltd QT1100A-isg r3.02/1105
figure 1.3 scanport only connection diagram+ without eeprom key9 key7 key4 22nf 22nf 22nf regulator QT1100A-as scano_0 scano_2 scano_3 scani_0 vdd key2 key8 key6 key5 key3 vunreg *10uf vdd 2.2k 2.2k 2.2k 2.2k 2.2k 2.2k 22nf 2.2k *4.7uf vdd *100nf 4.7k 2.2k 2.2k scani_2 scano_1 sync vdd scani_1 vdd 4.7k 4.7k key1 key0 4.7k 22nf 22nf 22nf 2.2k 22k 4.7k 22nf 4.7k 4.7k 4.7k vi vo g reset 22k 12mhz 3-pin resonator 22nf 22nf *one bypass capacitor to be tightly coupled to pins 36 and 17. follow regulator manufacturer's recommendations for input and output capacitors. 4.7k 4.7k 4.7k vdd scanport to/from host l q 11 copyright ? 2003-2005 qrg ltd QT1100A-isg r3.02/1105
2 device control & wiring 2.1 oscillator the QT1100A uses an external 12mhz resonator as its frequency reference. this frequency can be lowered for lower average power, however all functions will also slow down including response time and communications parameters. it is not advised to change the operating frequency without a good reason. the oscillator source can be from an external circuit, so that two or more circuits can share the same oscillator. if an external frequency source is used, it should be fed to osc1, pin 37. osc2 should be left open-circuit. 2.2 spread spectrum modulation the device features spread spectrum modulation of its acquisition bursts to dramatically reduce both rf emissions and susceptibility to external ac fields. this feature cannot be disabled or modified. spread spectrum modulation works together with the detection integrator (?di?) process to eliminate external interference in almost all cases. 2.3 cs sample capacitors the cs sample capacitors accumulate the charge from the key electrodes and determine sensitivity . (see section 2.4) the cs capacitors can be virtually any plastic film or low to medium-k ceramic capacitor. the ?normal? cs range is 2.2nf to 100nf depending on the sensitivity required; larger values of cs require higher stability to ensure reliable sensing. acceptable capacitor types for most uses include pps film, polypropylene film, and np0 and x7r ceramics. lower grades than x7r are not advised. the cs capacitors and all associated wiring should be placed and wired very tight to the body of the ic for noise immunity to very high frequency rf fields. see section 2.7. 2.4 sensitivity sensitivity can be altered to suit various applications and situations on a key-by-key basis. one way to impact sensitivity is to alter the value of each cs when the device is in ntm = 0 mode (see page 25); higher values of cs will yield higher sensitivity; each key has its own cs value and so can be adjusted independently. the setups block can also be used to alter sensitivity, using an external eeprom, serial communications, or both (section 4.1). sensitivity can also be increased by using bigger electrode areas, reducing panel thickness, or using a panel material with a higher dielectric constant (e.g. glass instead of plastic). in some cases the keys may be too sensitive. gain ca n be lowered by: a) making the electrode smaller, or, b) making the electrode into a sparse mesh using a high space-to-conductor ratio, or, c) by decreasing the cs capacitors (if ntm = 0). sensitivity trimming is usually done through a process of trial and error, using a range of ?standard fingers? made of earthed conductive rubber on the end of a plastic rod. 2.5 sensitivity balance a number of factors can cause sensitivity imbalances among the keys. notably, sns wiring to electrodes can have differing stray amounts of capacitance to ground, perhaps due to trace length differences or the presence of ground, power, or other signal wiring near the sns traces. increasing load capacitance (cx) will cause a decrease in gain. key size differences, and proximity to other metal surfaces can also impact gain. the keys may thus require ?balancing? to achieve similar sensitivity levels. the nthr parameter in the setups functions is one easy way to trim and balance key sensitivity (section 4.1). balancing can also be achieved by adjusting the cs capacitor values to achieve equilibrium. the rs resistors have no effect on sensitivity and should not be altered. load capacitance to ground (to boost cx) can also be added to overly sensitive channels to reduce gain; these should be on the order of a few picofarads. 2.6 power supply the power supply can range from 3.3 to 5.0 volts. if this fluctuates slowly with temperature, the device will track and compensate for these changes automatically with only minor changes in sensitivity. if the supply voltage drifts or shifts quickly, the drift compensation mechanism will not be able to keep up, causing sensitivity anomalies or false detections. the power supply should be locally regulated using a 3-terminal device. if the supply is shared with another electronic system, care should be taken to ensure that the supply is free of digital spikes, sags, and surges which can cause adverse effects. for proper operation a 0.1f or greater bypass capacitor must be used between vdd and vss; the bypass cap acitor should be routed with very short tracks to the device?s vss and vdd pins. 2.7 pcb layout and construction ground planes: the pcb should if possible include a copper pour under and around the ic, but not under the sns lines after the rsns resistors. ground planes increase loading capacitance (cx) on the sns lines and can dramatically degrade sensitivity. part placement: the resistors and capacitors associated with each key should be placed physically as close to the body of the QT1100A as possible, with the shortest possible trace lengths, to minimize the influence of external fields (see section 2.9.2). the QT1100A should be placed as close to the key electrodes as possible to reduce wiring lengths, to minimize stray capacitances on and between sns traces and to reduce interference problems. pcb cleanliness: all capacitive sensors should be treated as highly sensitive analog circuits which can be influenced by stray conductive leakage paths. qt devices have a basic resolution in the femtofarad range; in this range, there is no such thing as ?no-clean flux?. flux absorbs moisture and becomes conductive between solder joints, causing signal drift, false detections, and transient instabilities. conformal coatings will trap in existing amounts of moisture which will then become highly temperature sensitive. the designer should specify ultrasonic cleaning as part of the manufacturing process, and in cases where a high level of humidity is anticipated, the use of conformal coatings after cleaning to keep out moisture. l q 12 copyright ? 2003-2005 qrg ltd QT1100A-isg r3.02/1105
2.8 esd protection normally, only a series resistor is required for esd suppression. a 10k to 22k rsns resistor in series with each sense trace to each key is normally sufficient. the dielectric panel (glass or plastic) usually provides a high degree of isolation to prevent esd discharge from reaching the circuit. the rsns resistors should be placed close to and wired tightly to the chip, not the keys. if the cx load is high, rsns can prevent total charge and transfer and as a result gain can deteriorate. if a reduction in rsns increases gain noticeably, the lower value should be used. conversely, increasing the rsns can result in added esd and emc benefits provided that the increase in resistance does not decrease sensitivity. 2.9 noise issues 2.9.1 led traces and other switching signals digital switching signals near the sns lines will induce transients into the acquired signals, deteriorating the snr performance of the device. such signals should be routed away from the sns lines, or the design should be such that these lines are not switched during the course of signal acquisition (bursts). led terminals which are multiplexed or switched into a floating state and which are within or physically very near a key structure (even if on another nearby pcb) should be bypassed to either vss or vdd with at least a 10nf capacitor of any type, to suppress capacitive coupling effects which can induce false signal shifts. led terminals which are constantly connected to vss or vdd do not need bypassing. 2.9.2 external fields external ac fields (emi) due to rf transmitters or electrical noise sources can cause false detections or unexplained shifts in sensitivity. the influence of external fields on the sensor is reduced by means of the rsns series resistors. the cs capacitors and the rsns resistors form a natural low-pass filter for incoming rf signals; the roll-off frequency of this network is defined by - f r = 1 2 ? r sns c s if for example cs = 4.7nf, and rsns = 10k, the emi rolloff frequency is ~3.4khz, which is much lower than most noise sources (except for mains frequencies i.e. 50/60hz). rsns and cs must both be placed very close to the body of the ic so that the lead lengths between them and the ic do not form an unfiltered antenna at very high frequencies. pcb layout, grounding, and the structure of the input circuitry have a great bearing on the success of a design to withstand electromagnetic fields and be relatively noise-free. these design rules should be adhered to for best esd and emc results: 1. use only smt components. 2. keep all cs, rs, rsns, and the vdd/vss bypass capacitor components wired tightly to the ic. 3. place the QT1100A as close to the keys themselves as possible. 4. do not place electrodes or associated wiring near other signals, or near a ground plane. if a ground plane is unavoidable, keep the sns tracks very thin (e.g. 0.15mm) and relieve the ground plane widely around them (e.g. 5mm clear space on all sides). 5. do use a ground plane under and around the chip itself, back to the regulator and power connector (but not beyond the rs/cs/rsns networks). 6. to prevent cross interference, do not place an electrode or sns traces of one QT1100A near the electrode or the sns traces of another QT1100A or similar device, unless they are synchronized with a sync signal in a way that adjacent traces and keys do not have acquisition bursts on them at the same time. 7. keep the electrodes (and wiring) away from other traces carrying ac or switched signals. 8. if there are switched leds or related wiring near an electrode or sns traces (e.g. for backlighting of a key), bypass the switched traces to ground. 9. use a voltage regulator just for the QT1100A to eliminate noise coupling from other switching sources via vdd. make sure the regulator?s transient load stability provides for a stable, settled voltage just before each burst commences. 2.10 start-up time after a reset or power-up event, the device requires 400ms to read the eeprom, if one is connected, initialize the device, and start acquiring signals. after this time, the part will calibrate all keys. the calibration time depends on the burst spacing but is about 450ms for a burst spacing of 3ms. this time is proportional to the burst spacing (section 4.14). the burst spacing governs the time from the start of one key acquisition cycle to the next, and can be set via serial setups or via the external eeprom. thus, the total start-up time after a reset is about 850ms if the burst spacing is set to 3ms. the device will communicate immediately after the setup block is loaded (from eeprom. if any, or from defaults). 2.11 operating parameter setups the device features a setups block area in internal ram that holds numerous configuration parameters determin ing how the part will operate. each key can be configured individually for a wide variety of parameters as discussed in section 4. in addition, the device can be configured for the aks ? function which treats participating keys as a group in which only the key with the strongest signal will generate a response. standalone (with eeprom) setups: in standalone mode with eeprom, device setups are configured using an external 93lc46a byte-mode eeprom (see table 1.2, page 5). this part can be programmed separately using a commercially obtainable programm ing device then inserted into the circuit, or, it can be programmed using a QT1100A in serial mode via a pc interface with the 93lc46a in a socket so that it can be transferred to the target pcb. the eeprom contents and default values are detailed in table 4-1, page 31. the last eeprom entry should be a crc check byte. if the crc byte is set to 0xd6, the crc will be ignored. in standalone mode the eeprom must have the first byte in location 0 set to the value 0xd6 for the eeprom to be read. the rest of the setup table must follow, starting at location 1 in the eeprom. l q 13 copyright ? 2003-2005 qrg ltd QT1100A-isg r3.02/1105
without the eeprom the QT1100A will operate in a default mode, designed to accommodate most touch sensing requirements (section 2.12, below). serial mode setups: the two serial interfaces permit a host mcu to program control setups into the QT1100A on power-up or even during normal operation, allowing low cost reconfigurability. this is performed with a block of data, referred to as a setups block. the setups block must end with a crc check byte. if the optional 93lc46a eeprom is also used, the setups block will be stored locally so that there is no need to reload after each power-up. 2.12 standalone operation, no eeprom the device can operate in standalone mode without serial communications or eeprom using only its parallel scanport interface. (see table 1.3, page 6 and figure 1.3, page11) there are some minor differences in the default settings and behaviour in standalone mode without eeprom compared with other modes: 1. k2l is enabled on all keys* 2. sync is enabled (se = 1)* 3. no serial comms - crdy is always clamped low *these exceptions are noted in table 4-1, page 31. 2.13 eeprom functionality the serial eeprom is used to store setups information which alters the device behavior. if the eeprom is not used, the device uses default parameters to operate , or, customized parameters loaded into the device via serial interface. the eeprom?s functionality is not necessary when used with a serial interface. the host serial controller can send the setups to the QT1100A following each power-up. in a serial mode, the eeprom eliminates the need to send setups after each power-up since they are stored locally. the eeprom must contain the value 0xd6 as its first byte or it will not be read. the table on page 31 shows the contents required for this eeprom. a crc must be appended to the end of the eeprom table, or, the crc can be replaced by a 0xd6 code, in which case no crc checking will be performed (not recommended except as a development shortcut). a blank eeprom will be programmed properly when the host sends a setups block to the device. eeprom corruption is automatically detected every 2 seconds during normal run operation . if the eeprom is found to be corrupt or erased, the eeprom error flag is set in the device status byte (command 0xc2); the eeprom itself is not corrected. if the device is using serial communications, the host controller should reload the setups and then reset the device. if in a serial mode an eeprom is not installed, pin diee should be connected to vdd. 2.14 scanport interface the scanport functions as a ?legacy replacement? for a matrix scanned xy keyboard. single inputs (one-of-three) on scan_in lines result in a pattern of bits on scan_out pins depending on the keys that are active. if no keys are active the scan_out pins remain inactive. see connection pinlists, tables 1.1 and 1.2. all logic on the scanport is ?active high? for both scan_in and scan_out. the scanport maps to the scan_in and scan_out pins as per table 2.1. 0 0 key 9 key 8 scan in 2 key 7 key 6 key 5 key 4 scan in 1 key 3 key 2 key 1 key 0 scan in 0 scan out 3 scan out 2 scan out 1 scan out 0 table 2.1 - scanport i/o mapping the scanport is enabled if the cmode pin is strapped low . the uart is also enabled in this mode but it can be ignored ; if uart serial is not used, tx should be connected to vss. scanport latency: the latency of the scanport from scan_in to scan_out is 120s maximum. uart transfers do not affect this response time . scanning software has to take this delay into account, i.e. it should not expect the scan_out pins to be stable until 120 s after setting the scan_in pins. one easy way to use the scanport is to read the scanport before changing the scan_in signals. normally, scan_in should be changed to a new state every 1 ~ 2ms. faster scanning than this will not result in a perceptibly faster response time. therefore, if the scan_out lines are read immediately before changing the scan_in signals, the host controller will not have to wait for the 120s scanport latency. system response time: the setting of the two detection integrators (see section 4.9) strongly affects the basic device response time. the host?s scan rate adds to this time. if the basic QT1100A response time is set to 80ms, and the host completely scans the device every 50ms, the total response time can be a very slow 130ms. one way to maintain good response time while minimizing host activity is to have the host monitor the led/stat pin, perhaps via interrupt, and service the scanport only when the led/stat pin becomes active. (see section 4.8, page 27) sleep/wake function: sleep/wake can only be used in conjunction with a serial mode which sets the sleep state via a command, and so sleep is not possible in scanport mode without a serial interface. sync mode with scanport: sync mode can be enabled using an eeprom having the correct setups; sync mode also works in standalone mode without an eeprom (see also section 4.12). in sync mode the acquire bursts are synchronized to the external clock source; the scanport will operate correctly while the device is waiting for a sync edge. 2.15 start-up sequencing after power-up or reset the flag ?reset occurred ? will be set. the user can read this flag with command 0xc2. this flag can be reset by issuing a ?0xc2 0xc7? command sequence. if an eeprom is installed and the eeprom?s crc does not match its contents, or the first byte is not 0xd6, the error flag ?eeprom error? will be set. in this case, the default setup settings will be used but the eeprom contents will stay unchanged. 2.16 error detection and reporting a ?major error? is one where an enabled key signal falls below lbll (section 4.13) or rises above a value of 4095, or where there is a crc error in ram or eeprom setups. the l q 14 copyright ? 2003-2005 qrg ltd QT1100A-isg r3.02/1105
former can occur if the cs capacitor fails or there is a short in the sns circuit; if this happens, the affected key is shut down immediately and the key is switched off. keys that are intentionally disabled will not burst, and so cannot show an error. in standalone mode with no eeprom present (scanport mode), keys are disabled by strapping the sns pins to ?unused? settings (table 1.1 page 4), and this will not generate a ?major error?, unless the error occurs after the part has gone through power-up calibration successfully without detecting that the key is disabled via sns pin configuration. in any mode that uses an eeprom or uses either uart or spi communications, keys must be disabled by setting the nthr parameter to zero for the key(s) (section 4.1). if in eeprom or serial mode a key is disabled via sns pin wiring only, it will be classified as a ?major error?. 3 serial operation there are two serial interfaces in the QT1100A: uart, and spi. uart provides a simple solution using well known asynchronous signalling. many mcus contain uart or usart blocks which are perfectly suited to this mode. mcus without a uart hardware function can easily use a firmware uart function in most cases. the chief advantage of uart mode is wiring simplicity: only 3 wires, (tx, rx, and crdy) are required. spi communications are based on the well known synchronous interface used extensively between microcontrollers and peripherals. the QT1100A uses slave-only spi mode. this interface does not require an accurate clock rate, and can operate faster than uart mode. however, spi operation requires 5 wires. the host device always initiates communications sequences; the QT1100A is incapable of chattering data back to the host. a command from the host to the QT1100A always ends in a one or more byte response from the QT1100A. some transmission types from the host require the use of a crc check byte to provide for robust communications. this command/response design is intentional for fmea purposes so that the host always has total control over the communications with the QT1100A. effectively this behavior forces designs to have inherently self-checking ?loop back? characteristics. system response time: the setting of the two detection integrators (see section 4.9) strongly affects the basic device response time. the serial poll rate adds to this response time. if the basic QT1100A response time is 80ms, and the host polls the device every 50ms, the total response time can be a very slow 130ms. normally, the host should poll the QT1100A every ~10ms to minimize delay ?stacking?. to minimize delays further, the command 0xc9 can be used (?quick 1st key?; see section 3.5.14) instead of 0xc0. one way to improve speed while minimizing host activity is to have the host monitor the led/stat pin, perhaps via interrupt, and service the device with a 0xc0 or 0xc9 command only when the led/stat pin becomes active. (see section 4.8) 3.1 uart interface uart mode allows a host device to communicate conveniently over two serial wires asynchronously, with a handshaking line (crdy) to provide bidirectional data flow control. the uart mode operates in the same way and with the same protocol and commands as the spi interface. uart mode is selected by strapping the cmode pin low. uart mode and scanport mode can operate together. if only uart mode is desired, the scan_in pins need to be grounded. if only the scanport is used, the uart can be ignored. an unused rx line should be connected directly to vdd. uart transmission parameters are (fosc = 12mhz): baud rate options: 4800, 9600, 19.2k, 28.8k start bits: 1 data bits: 8 parity: none stop bits: 1 uart operation with scanport: scanport and uart operation can be used together. (see section 2.14) 3.1.1 tx pin the tx pin has an open-drain drive to allow bussing with other similar parts. the tx line can thus be shared with other uart based peripherals such as a second QT1100A. tx must be pulled high to vdd with a resistor in uart mode. the resistor value will depend on the total amount of stray capacitance on tx - more capacitance will require lower values of pull-up resistor, especially at higher baud rates. the risetime of the signals on this line should be 1/10th of the bit width, i.e., if running at 9600 baud, the bit width is about 100s, and the risetime should be 10s or less. in most cases, a 47k resistor is low enough, however this should be confirmed using an oscilloscope. an unused tx pin should be connected to vss. 3.1.2 sleep/wake operation in uart mode the device can be put into sleep mode with a serial command (0x05). the device can sleep for up to 700ms; some time after this it will self-reset. the wake and rx functions are on the same pin, which allows a host to conveniently wake the device with a dummy character (e.g. 0x00 null) before communicating with it. wake operates on the falling edge; the negative-going level must be at least 40s wide to be recognized. see also section 3.4.6. 3.1.3 crdy operation in uart mode the crdy serial handshake pin is open-drain and requires a 10k ~ 220k pull-up to vdd. either the host or the QT1100A can pull down on this line to stop data flow (wire d-and logic). if crdy is high the communications can flow in either direction. the host should obey this control line or overruns and transmission errors will occur in the device. host-to-QT1100A uart crdy behavior: if the crdy line is released by the host but the crdy line stays low, this means the QT1100A is busy and cannot accept communications. the host must wait for the crdy line to float high again before it can send the byte. if the crdy line happens to go low again just as the host is about to send a byte, the host has a 10s grace period in which it can still initiate the transmission. this is acceptable for most mcu types, however even fast pcs operating under windows have a difficult time responding within the 10s grace period and this can result in frequent transmission errors. QT1100A-to-host uart crdy behavior: when the QT1100A needs to send data back to the host, it will release the crdy line (if not already released) and wait for it to float l q 15 copyright ? 2003-2005 qrg ltd QT1100A-isg r3.02/1105
high before sending a byte. if the host is busy and cannot accept data, it should clamp crdy low until it is ready. before each return byte is sent, the QT1100A will check crdy in this manner and wait until the host is ready before sending. the host should allow a 10s grace period in which it can still accept data from the QT1100A after it releases crdy high, to allow for any delays in the response from the sensor. crdy / burst behavior: the pacing of crdy and the transmission of uart data are interleaved with acquisition bursts. the QT1100A cannot send or receive data during a burst or for a short time thereafter. crdy is forced low by the QT1100A when a burst is taking place and communication is not possible. at the fastest burst spacing, there is at least a 250s window of time between bursts when communications can take place and crdy is high. if a serial transmission from QT1100A to host is occurring when a burst should be starting, the communications takes precedence and the next acquisition burst is delayed. 3.2 spi operation refer to page 38 for timing diagram. the spi mode allows a host device to communicate conveniently using four control lines synchronously, with a crdy handshaking line to provide control flow. the spi mode operates in the same way and with the same protocol and commands as the uart interface. however whereas the uart mode permits the QT1100A to send back responses to the host under its own volition, the spi mode is a slave mode only requiring the host to always generate the shift clock. where a response is expected back from the QT1100A, the host can shift over a dummy null (0x00) command to the QT1100A which will be ignored. the host should not overlap commands with responses. thus, if there are two expected response bytes to a command, the host can send and shift back the following bytes: 0x55 (see below*) command_b 4 response_2 to a null 3 response_1 to a null 2 0x55 (see below*) command_a 1 QT1100A response host shift # spi transmission parameters are (fosc = 12mhz): transmission mode: slave-only clock rate: 100khz max clock duty cycle: 50% data bits: 8 clock idle: high clock shift out edge: falling clock shift in edge: rising delay from shift in edge: none *note that the QT1100A returns a 0x55 dummy byte with a host command. if a command is not recognized, the response on the next shift will be 0x55. 3.2.1 multi-drop spi capability in spi mode the do pin floats while /ss is high to allow the spi lines to be shared with other devices. a 10k ~ 20k ohm pull-up resistor should be used on this pin to prevent do from freely floating. when used with other similar devices, each QT1100A part should have its own /ss and crdy connections back to the host controller; the other spi lines can all be shared. 3.2.2 sleep/wake operation in spi mode the device can be put into sleep mode with a serial command (0x05). the device can sleep for up to 700ms; some time after this it will self-reset. wake operates on the falling edge; the negative-going level must be at least 40s wide to be recognized. the wake pin can be connected to /ss, and the host can then wake the device from sleep using a >40s negative dummy pulse on /ss. see also section 3.4.6. 3.2.3 crdy operation in spi mode crdy is an open-drain line requiring a 10k ~ 220k ohm pull-up resistor. the QT1100A will pull down on this line to stop data flow from the host. the QT1100A does not respond to the host pulling crdy low in spi mode, since the host is always in control of all data transmissions. crdy is unidirectional (QT1100A to host) in spi mode. the host must wait for crdy to float high before it can clock the spi interface. if crdy happens to go low again just as the host is about to clock data, the host has a 10s grace period in which it can still initiate /ss (slave select) even though crdy has already gone low. crdy / burst behavior: the pacing of crdy and the transmission of uart data are interleaved with acquisition bursts. the QT1100A cannot send or receive data during a burst or for a short time thereafter. crdy is forced low by the QT1100A when a burst is taking place and communication is not possible. at the fastest burst spacing, there is at least a 250s window of time between bursts when communications can take place and crdy is high. similarly, if the burst duration exceeds its timeslot, the device will ensure that there is an additional 250s appended to the burst to allow for communications. if a serial transmission is occurring when a burst should be starting, the communication takes precedence and the next acquisition burst is delayed. therefore, the 250s should be viewed as a minimum which can expand to meet the needs of a single byte transmission. additional bytes will usually occur in the next timeslot. 3.3 communication error handling if a communications error takes place, the host should recover by issuing a ?return last command? command (0xc7) at least twice to make sure the QT1100A and host are communicating properly with each other. 3.4 control commands control commands are used to place the device into special modes or cause the device to reset, calibrate or run. (see summary table 3-1, page 23) 3.4.1 null command - 0x00 (spi only) this command is used primarily to shift back data from the QT1100A in spi mode. where a response is expected back from the QT1100A after a command, the host should shift over a null for each expected byte. l q 16 copyright ? 2003-2005 qrg ltd QT1100A-isg r3.02/1105
since the host device is always the master in spi mode, and data are clocked in both directions, the null command is required to act as a placeholder where the requirement is to get data back from the QT1100A. see also section 3.2. in uart mode there is no response whatsoever to a null command. 3.4.2 enter setups load mode - 0x01 this command is used to load the setups block into the device over either serial interface. see table 4-1 on page 31 for reference. the command must be repeated 2 times within 100ms or the command will be aborted (not reset); the repeat of the command must be sequential without any other intervening command or even a null. 250s worst case after receipt of the second 0x01, the device will start to send back the response byte 0x53 (signalled using crdy as always, i.e. the response could be delayed beyond 250s by the host itself, either via a late shift operation in spi mode or via holding crdy low in uart mode). if no 0x53 is returned, the command was not properly received; the host should recover by issuing a ?return last command? command (0xc7) at least twice to make sure the QT1100A and host are communicating properly with each other, and then the 0x01 commands should be sent again. from this point on the host should send the setups block including the ending crc byte as a stream to the QT1100A, without interruption, paced only by the crdy line. during this time the chip suspends its normal acquisition bursts. the time between bytes can be from 10s to a limit of 100ms. if a data timeout occurred in the block load (the time between any two sequential block data bytes exceeded 100ms) a response of 0xf1 will immediately be attempted back to the host, the setup block sequence will be aborted, and the chip will reload the setup block from the eeprom (if available and correct) or from ?factory defaults?. a device reset will automatically occur if the QT1100A does not receive a further command (any of 0x01, 0x02, 0x03 or 0x04) within 1s after the block sequence has suspended due to a timeout error. the host should listen for a 0xf1 response while shifting the setups block to terminate and restart the setups load sequence if required. note that in spi mode, all responses must be shifted out with nulls shifted over by the host. eeprom not present: if no eeprom is installed and diee is tied to vdd, the QT1100A will check the crc and reply with a response byte: 0xf0 - crc not ok, and as a result block load failed 0xf1 - transfer timeout; time between bytes >100ms 0xfe - block loaded ok, crc is ok in the case of either 0xf0 or 0xf1, the QT1100A will load ?factory defaults? into the device (when no eeprom is present). with no eeprom present, the delay between the crc byte sent to the QT1100A and the response back from the QT1100A is 800s maximum (signalled using crdy). eeprom present: with an eeprom installed, the device will check the crc and if valid, start programming the eeprom with the new setup block, and check that the eeprom is written correctly. it will respond as follows: 0xf0 - crc is not ok, and as a result block load failed 0xf1 - transfer timeout; time between bytes >100ms 0xf2 - block loaded ok, but eeprom write failed 0xfe - block loaded ok, crc is ok, eeprom write ok (0xfe response requires up to 370ms due to eeprom write time - this is dependent largely on the eeprom?s write time specification) if there is no response from the device within 370ms after the block has been completely sent , the command was not properly received and the device should preferably be reset using the rst pin before attempting the command again. only if the entire setup block is received without error and the crc is ok (or 0xd6 for testing; see below) will the setups information be recorded to eeprom. at the end of the full command sequence the device remains suspended (acquire bursts are stopped) until a setups, run, cal, or reset command is received (0x01, 0x02, 0x03, or 0x04). if one of these commands is not received within 1s after the block is loaded and the response byte is generated , the part resets itself, enters cal mode, and then runs automatically. if there was an error in the setups load operation, the device will run either with ?factory defaults? (if there was a 0xf2 error) or with previously stored eeprom data (if there was a 0xf0 or 0xf1 error). crc note: the 0x01 command requires that the ending crc byte is calculated by the host on the data block itself without the 0x01 command itself being folded in to the crc. this is a notable exception to the use of crcs in this device. other commands ending in a crc fold in the command byte itself as the first byte in the crc calculation. dummy crc for testing: for testing purposes, a dummy crc byte, of value 0xd6, can be placed at the end of the setups block which is always accepted by the QT1100A even though it is ?wrong?. while a 0xd6 value will inhibit crc checking, the QT1100A will actually compute and record the correct crc value into the eeprom (if present). should an actual crc calculation result in a 0xd6 (probability = 0.39%) and crc checking is required, the designer should change one of the unused bits shown in the setup table (page 31) to cause the crc to be something else. after a setups load: after a successful setups block load, there are four basic options: 1. run the device via the 0x02 command, i.e. without the benefit of a recalibration, or, 2. calibrate the device via the 0x03 command, in which case the device will calibrate all keys and run again, or, 3. reset the device using the 0x04 command, or, 4. wait 1 second for the device to enter self-reset. changes to ndcr, nrd, aks, ek, k2l, pdcr, prd, pthr, phys, ledp, lbll, keyo, br or bs do not require a recalibration to take effect, and it is faster to just issue a 0x02 run command after the 0x01 is complete. changes to nthr, nhys, ndil, fdil, and ntm should be followed with a 0x03 cal command. changes to se or sync should be followed with a device reset command, rst pin reset, or 1s timeout reset to allow the new parameters to properly take effect. l q 17 copyright ? 2003-2005 qrg ltd QT1100A-isg r3.02/1105
3.4.3 enter run mode - 0x02 this command is used only after a setups load command (0x01) has completed to get the device to run as a sensor, without any key calibration. this is useful to make running changes, for example in drift compensation rates or threshold levels, without disturbing key calibrations. the command must be repeated 2 times within 100ms or the command will fail; the repeated command must be sequential without any intervening command , not even a null. after the second 0x02, the QT1100A will reply with the character 0xfd when the part begins to run as a sensor. the delay in responding to the second 0x02 with 0xfd is 250s maximum (signalled using crdy). if no 0xfd is returned, the command was not properly received; the host should recover by issuing a ?return last command? command (0xc7) at least twice to make sure the QT1100A and host are communicating properly with each other, and then the 0x02 commands should be sent again. 3.4.4 enter cal mode - 0x03 this command is normally used only after a setups load command (0x01) has completed to get the entire device to calibrate and run as a sensor. note that on normal power-up or reset, the device will automatically enter cal mode regardless, and then run normally. therefore the only time this command is required is when the part is suspended after a setups load, or, if there is a need to recalibrate all keys at one time during normal running. the 0x1k command is more efficient for recalibrating individual stuck keys if desired (section 3.4.7). the 0x03 command must be repeated 2 times within 100ms or the command will fail; the repeating command must be sequential without any intervening command , not even a null. after the second 0x03 from the host, the QT1100A will reply with the character 0xfc within 450s if the command has been accepted. after the 0xfc response, the device will initiate calibration of all keys in parallel. the host can check the progress of calibration by issuing a 0x8k command on the highest enabled key (e.g. key #9); all the keys being calibrated by 0x03 will have finished calibrating when the highest key number is done. the time required to calibrate all 10 keys is 15 complete acquire cycles, or 15 x 10 keys = 150 timeslots. if the burst spacing is 4ms, then cal will require 600ms to calibrate all 10 keys. disabled keys do not reduce this time. afterwards, the host can check error flags to find which key(s) failed during calibration , if any, for example using command 0xc2 (section 3.5.7) or 0xc5 (section 3.5.10). this might happen if there is a component failure , short or open circuit on the pcb. if no 0xfc is returned, the command was not properly received; the host should recover by issuing a ?return last command? command (0xc7) at least twice to make sure the QT1100A and host are communicating properly with each other, and then the 0x03 commands should be sent again. 3.4.5 force reset - 0x04 this command is used to cause the part to reset, in the same way as a hardware /rst signal. this command must be repeated 2 times within 100ms or the command will fail; the repeating command must be sequential without any intervening command , not even a null. after the second 0x04 from the host, the QT1100A will reply with the character 0xfb within 250s to indicate that it has been properly received. if no 0xfb is returned, the command was not properly received; the host should recover by issuing a ?return last command? command (0xc7) at least twice to make sure the QT1100A and host are communicating properly with each other, and then the 0x04 commands should be sent again. after the part resumes operation , it will set the ?reset occurred? flag (see section 2.15) to indicate there was a power-up event, and it will go through a complete c al mode automatically and then run and sense keys normally. the device will calibrate and run after a delay of 100ms + 150 burst spacings, which could be up to 1.05s on 7ms burst spacings. while calibrating, the QT1100A can communicate serially and the user can track the progress of ongoing calibrations using command 0x8k. 3.4.6 sleep - 0x05 this command is useful to allow low average operating power when in standby mode or when fast response time is not required. during sleep, the device consumes only a few microamps of current. using sleep mode, it is possible to get average current consumption down to 100a while having the part run with reduced response time. actual average current drain will be a function of the ratio of running time to sleep time. the 0x05 command must be repeated 2 times within 100ms or the command will fail. after the second 0x05 from the host, the device will reply with the character 0xfa within 250s. the device will then enter a sleep mode until awakened by a negative edge or negative pulse on the wake pin (pin 22), at least 40s, wide or via a hardware reset on the rst pin. note that if the device is reset, it will recalibrate on power-up, which is usually not desirable . if the device wakes via the wake pin, it will resume operation in the same state from which it went to sleep. if no 0xfa is returned, the command was not properly received; the host should recover by issuing a ?return last command? command (0xc7) at least twice to make sure the QT1100A and host are communicating properly with each other, and then the 0x04 commands should be sent again. if the device is not awakened intentionally within 700ms of entering sleep, the device can go into self-reset causing the internal states and data to be lost , and a recalibration to be performed. in uart mode, the QT1100A can be awakened with a null (0x00) byte. in spi mode, the QT1100A can be awakened by connecting pin /ss to wake and sending an empty /ss pulse from the host to the qt. wake time: the device requires ~160us from the wake input to resumption of normal sensing and communications. 3.4.7 cal key ?k? - 0x1k calibrates only key k, where k = {0..9}. example: the command 0x14 causes key 4 to calibrate. this command functions the same as the 0x03 cal command (section 3.4.4, above) except this command only affects one key . this command must be repeated 2 times within 100ms or the command will fail; the repeating command must be sequential without any intervening command , not even a null. 0x1k returns 0xf8 if the command has been accepted and will be processed. this response can come up to one burst l q 18 copyright ? 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timeslot after the second 0xf8 has been received. the user can then track the progress of the key calibration with the 0x8k command (section 3.5.4). if no 0xf8 is returned, the command was not properly received; the host should recover by issuing a ?return last command? command (0xc7) at least twice to make sure the QT1100A and host are communicating properly with each other, and then the 0x1k command should be sent again. the chosen key ?k? is recalibrated in its normal burst timeslot; normal running of the part is not interrupted and all other keys operate correctly throughout. this command is for use only during normal operation to try to recover a single key that is stuck or has not calibrated correctly. it is possible to issue several 0x1k commands to several keys sequentially, however the 0xf8 return value should be received back from a prior 0x1k command before a new 0x1k command is issued. 3.5 status commands status commands are used to evoke a response from the QT1100A, for example to return signal values or to get key status. see summary table 3-2 on page 24. 3.5.1 signal for 1 key - 0x2k returns the raw signal for key k, where k = {0..9}. example: the command 0x25 addresses key 5. the value is a 16-bit number and no crc is appended to the return, so the return data should not be considered secure under fmea rules. the valid return number range is from 0..4095. the high byte is returned first. 3.5.2 reference for key ?k? - 0x4k returns the reference level for key k, where k = {0..9}. example: the command 0x48 addresses key 8. the value is a 16-bit number and no crc is appended to the return, so the return data should not be considered secure under fmea rules. the valid return number range is from 0..4095. the high byte is returned first. 3.5.3 detect integrator for key ?k? - 0x6k returns the detect ?normal? detect integrator (?di?) for key k, where k = {0..9}. example: the command 0x63 addresses key 3. the value is contained in the lower 4 bits of an 8-bit character, i.e. in the range from 0..15; no crc is appended to the response, so the return data should not be considered secure under fmea rules. 3.5.4 status for key ?k? - 0x8k returns the status bits for key k, where k = {0..9}. example: the command 0x87 addresses key 7. the return value is contained in a single 8-bit character. a crc is appended to the return; this crc includes the command 0x8k itself as the first byte in the crc calculation. the return bits are as follows: 1 = this key has a cal error (non-volatile) 2 1 = this key is undergoing calibration (volatile) 3 1 = this key is in process of detection (but not yet reported as having detected) (volatile) 4 unused 5 unused 6 1 = this key is in detect (volatile) 7 description bit # 1 = this key is disabled due to a setup configuration or due to an extreme condition (non-volatile) 0 1 = this key is experiencing extreme signal conditions (non-volatile) 1 bit_7: 1 = active key. the key is indicating a confirmed touch. this bit is set or cleared dynamically depending on the state of the di counter for each key. this bit is will self-clear when touch is no longer detected. bit_4: 1 = detection pending. the key is in the process of trying to confirm a detection (the signal is below nthr), but has not yet reported as active. normally this flag is only used for test purposes. this bit will self-clear when the key falls out of this state. bit_3: 1 = calibration in progress. the key is in the process of calibration. this bit will self-clear when the calibration is complete. bit_2: 1 = cal error. there was an error on this key the last time it attempted a calibration. this means an overflow (signal >4095) or underflow (see section 4.13, page 29) occurred during a cal cycle for that key. this bit is determined only after a cal of the key in question (either via cal 0x03 or 0x1k commands). after reset, these bits are cleared for all 10 keys and are set (or not) after the subsequent cal of the key(s) in question. bit_2 is non-volatile and can only be cleared by recalibration or a device reset. note that keys with faulty calibration stop operating and the corresponding acquisition bursts are disabled. bit_1: 1 = extreme signal. the signal level currently on this key is either too high or too low for normal operation, i .e. if the real-time signal falls below the minimum signal level defined by lbll (see section 4.13, page 29), or if {signal >4095} counts. bit_1 is non-volatile, that is, the bit will remain '1' even if the problem is removed, until the key is recalibrated or the device is reset. a key with bit 1= 1 is automatically disabled and its acquisition burst is disabled. this type of error may occur because the key either lacks a working rs/cs circuit or there is a short or open circuit. bit_0: 1 = key disabled. this can be due to an intentional setups disable (nthr setup in the setup block is set to 0) or, there is a problem with the sns pins (see bit_1 above). this bit is persistent (non-volatile) and will not clear unless the key is re-enabled via a new setups block load. 3.5.5 report 1st key - 0xc0 reports the first or only key to be touched, plus indicates if there are yet other keys that are also touched. the return bits are as follows: key bit 0 0 key bit 1 1 key bit 2 2 key bit 3 3 # keys in detection, low bit 4 # keys in detection, high bit 5 reserved: can report 0 or 1 6 logical-or of all error types 7 description bit # l q 19 copyright ? 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bit_7: 1 = indicates if there are any errors anywhere in the part, of any type. bits_4,5: encode for the number of keys in detection: 01 = one key 10 = two keys 11 = 3 keys or more bits_0..3: encode for the first detected key in range 0..9. if there are 2 or more keys in detection, the host controller should also interrogate the part via the 0xc1 command to read out all key detections. 0xc0 should be the dominant interrogation command in the host interface; further commands like 0xc1, 0xc2, 0xc5 etc. can be issued if the response to 0xc0 warrants it. a crc byte is appended to the response ; this crc includes the command 0xc0 itself as the first byte in the crc calculation. see also the very similar 0xc9 command, page 21. 3.5.6 report all keys - 0xc1 returns two bytes which indicate any and all keys in detection, as a bitfield, one bit per key. the first byte returned is the msbyte. key 0 reports in lsbyte bit 0. key 9 is reported in msbyte bit 1. the valid range of reporting is from 0..0x03ff (i.e. the bottom 10 bits). a crc byte is appended to the response ; this crc includes the command 0xc1 itself as the first byte in the crc calculation. 3.5.7 device status - 0xc2 this command returns a byte response which indicates the general device status. the return bit flags of the byte are as follows: 1 = cal error(s) (non-volatile) * 0 1 = crc error in ram (non-volatile) * 1 1 = crc error in eeprom (non-volatile) * 2 1 = sync error (non-volatile) 3 1 = extreme signal on one or more keys (non-volatile) * 4 1 = reset occurred (non-volatile) 5 1 = eeprom error (non-volatile) 6 1 = key(s) are detecting (volatile) 7 description bit # *these error types are considered major errors and will cause a forced output on a chosen key or keys if ek mode is set (section 4.7). in standalone mode (only scanport active and no eeprom present), an extreme signal on a key disables the key and is not considered a major error. bit_7 = 1: keys active. there are one or more keys in detection. this bit self-clears when there are no keys in detection. bit_6 = 1: eeprom error. eeprom is not attached, or eeprom first byte is not 0xd6, or, the crc of the eeprom?s setup block is not correct. if the eeprom is absent and diee is connected to vdd, an error will be reported in this bit. this bit can be reset only by a device reset or by the serial command sequence ?0xc2 0xc7?. see note below. bit_5 = 1: reset occurred. a reset event occurred. the bit can only be reset by the sequence ?0xc2 0xc7?. see note below. bit_4 = 1: extreme signals. there are one or more keys with an out-of-bounds signal condition. this bit is the logical-or of all 10 error flags from 0x8k bit 1 (extreme signal error). the bit can be reset only by a device reset or by a successful key recalibration. bit_3 = 1: sync error. there has been a sync error, i.e. a sync pulse was not found for ~1s or more. if the sync pulses are restored, this error bit is not automatically cleared. the bit can be reset only by device reset or by the sequence ?0xc2 0xc7?. see note below. bit_2 = 1: crc eeprom error. there has been a crc error in eeprom (if an eeprom is installed). this is computed approximately once per second. the bit can be reset only by device reset or by the sequence ?0xc2 0xc7?. see note below. bit_1 = 1: crc ram error . there has been a crc error in ram. this is computed approximately once per second. the bit can be reset only by device reset or by the sequence ?0xc2 0xc7?. see note below. bit_0 = 1: cal error(s). there was at least one calibration error during the last calibration event. this bit is the logical-or of all 10 bit_2 error flags readable via command 0x8k (cal error; see section 3.5.4). bit_0 is cleared only when all the cal errors are cleared, which can happen only if the problem key(s) have been recalibrated properly. a crc byte is appended to the response ; this crc includes the command 0xc2 itself as the first byte in the crc calculation. note: the 0xc7 used to clear flag bits can immediately follow the 0xc2 command; it is not required to issue the 0xc2 command a second time before issuing the 0xc7. 3.5.8 eeprom crc - 0xc3 this command returns the 8-bit crc calculated from the eeprom contents (if one is installed). the crc is calculated according to the algorithm shown in section 6. a crc byte is appended to the response ; this crc includes the command 0xc3 itself as the first byte in the crc calculation. if this crc does not agree with the expected result, the device should be reloaded with the setups command (0x01). if an eeprom does not exist (and pin diee is tied to vdd as recommended) the returned value will be 0x00. 3.5.9 ram crc - 0xc4 this command returns the 8-bit crc calculated from the ram (volatile) setup block in the device. the crc is calculated according to the algorithm shown in section 6. a crc byte is appended to the response ; this crc includes the command 0xc4 itself as the first byte in the crc calculation. if this crc does not agree with the expected result, the device should be reloaded using setups command 0x01 (if there is no eeprom) or, the device should be reset (if there is an eeprom). if the latter case, and a reset does not fix the problem, the eeprom should be reloaded using the 0x01 command. 3.5.10 error flags for group - 0xc5 error flag bits are set in the response to this command if the corresponding key is in condition {signal4095}, i.e. there is a short or open circuit, or there is a component failure. the error flag bits are non-volatile, that l q 20 copyright ? 2003-2005 qrg ltd QT1100A-isg r3.02/1105
is they persist even after the hardware problem is cleared, and are only re-evaluated when the key(s) or device is recalibrated or reset. the error bits are the logical-or of any error type for each key, i.e. either a cal error or a running key error. errors resulting from crc checks and sync errors are not contained in this command. the valid range of reporting is from 0..0x03ff (i.e. the bottom 10 bits). a crc byte is appended to the response ; this crc includes the command 0xc5 itself as the first byte in the crc calculation. 3.5.11 internal code - 0xc6 this command returns an internal diagnostic code for use by quantum. a crc byte is appended to the response ; this crc includes the command 0xc6 itself as the first byte in the crc calculation. 3.5.12 return last command - 0xc7 this command returns the last received command character, in first complement (inverted). if the command is repeated twice or more, it will return the first complement of 0xc7 i.e. 0x38. if a prior command was not valid or was corrupted, it will return the bad command (inverted) as well. when this command is used immediately after command 0xc2 it will reset any active, clearable device status flags - see section 3.5.7, above. no crc is appended to the response. 3.5.13 dump setups block - 0xc8 this command causes the device to dump the entire setups block back to the host. a crc is appended to the response but this crc is the same as the ram or setups block crc, i.e. the command 0xc8 is not folded into the crc calculation, only the setups data are used in the calculation. 3.5.14 quick report first key - 0xc9 this command is virtually identical to the report first key command 0xc0 (see section 3.5.5), but does not append a crc, giving a simpler 1-byte response than offered by 0xc0. this command can be used to speed up the communication between the host and the QT1100A chip when used as the predominant query command. for fmea purposes, if this command does report an active key, then the 0xc0 command (and others) can be issued subsequent to the 0xc9 to validate the result. in many cases, fmea checking is not required, and the single-byte response of 0xc9 is sufficient. 3.6 command sequencing to interface with a host, the flow diagram of figure 3-1 is suggested. the setups block should normally just use the default settings except where changes are specifically required, such as for sensiti vity, timing, or aks changes. the circles in this drawing are communications interchanges between host and sensor. the rectangles are internal host states or processing events. a communications failure occurs when the device fails to respond in the allotted time, the response crc is incorrect, or the response is inappropriate. in these cases the host should just repeat the command. the control flow will spend 99% of its time alternating between the two states within the dashed rectangle. if a key is detected, the control flow will enter ?key detection processing?. an enhancement might be the substitution of the 0xc9 command for the 0xc0 command to reduce communications overhead, at least for times when the part is not sensing any touches. the ?stuck key detected? branch (bottom left) is optional, since the device contains the max on-duration timeout function and so can recalibrate the stuck key automatically. however, the host can recalibrate stuck keys with greater flexibility if the recalibration timeouts are set to infinite and the host recalibrates them under specific conditions. error handling takes place whenever an error flag is detected, or the device stops communicating (not shown). the error handling procedure is up to the designer, however normally this would entail shutting down the product if the error is serious enough (for example, a key has failed). in serial systems with an eeprom, it is not necessary to send the setups block to the QT1100A each time, as the setups will be stored locally. however it is prudent to check the eeprom crc to be sure it has not become corrupted. the ?last command? command can be used at any time to clear comms error flags and to resynchronize failed communications, for example due to timing errors etc. l q 21 copyright ? 2003-2005 qrg ltd QT1100A-isg r3.02/1105
figure 3-1 suggested serial flow l q 22 copyright ? 2003-2005 qrg ltd QT1100A-isg r3.01/0505 0xc3 eeprom crc check 0xc1 report all keys only 1 key in detect 0x1k cal key 'k' key detection processing no key, no error m m m m 2 keys detected crc mismatch 0xc2 get general status extreme signal, or cal error, or comms crc error, or multiple or repeating errors power on or reset stuck key detected 0xc5 get errors for all keys any error flag (highest precedence) calibration error done keys ok note: crc errors or incorrect responses should cause affected transmissions to retry internal host process comms with qt 0xc2, 0xc7 clear 'reset' flag eeprom present no eeprom crc ok ram or eeprom crc error 0x01 load setups block error handling non-critical error (e.g. comms crc error) ~10ms delay 0xc9 or 0xc0 report 1st key 0x03 cal all
table 3-1 control commands commands are divided into two types: control commands, which force the device into various modes or are used for serial communi cations management, and status commands which report back with information about the device or the sensing process. used in normal running mode to calibrate one specific key. normal sensing of other keys not affected. calibration takes place in the key?s normal timeslot. returns 0xf8 to acknowledge command was received and the requested calibration will take place. 0xf8 1 2 force calibration of key #k where k= 0..9 command must be repeated 2 times within 100ms to execute or it will fail. cal key ?k? 18 0x1k returns 0xfa to acknowledge command; sleeps in low power mode, wakes on wake pin; returns 0x05 after wake. 0xfa + 0x05 2 2 enter sleep. command must be repeated 2 times within 100ms to execute or it will fail. sleep 18 0x05 returns 0xfb to acknowledge command, then resets device. after reset, part restarts, recalibrates, and runs automatically (same as any other type of reset). 0xfb 1 2 force device to reset. sends back ?0xfb? to acknowledge prior to reset. command must be repeated 2 times within 100ms to execute or it will fail. reset 18 0x04 returns 0xfc after second 0x03 is received. check on progress of each key using 0x8k commands. 0xfc 1 2 force device to enter cal mode to recalibrate all keys; enters run mode afterwards automatically. command must be repeated 2 times within 100ms to execute or it will fail. cal all 18 0x03 returns 0xfd after the second 0x02 is received. 0xfd 1 2 enter run mode without benefit of calibration. command must be repeated 2 times within 100ms to execute or it will fail. run 18 0x02 returns 0x53 after second 0x01 is received. during or after block load; returns 0xfe if pass, or, 0xf0 if crc fail, or, 0xf1 if 100ms timeout between bytes, or, 0xf2 if eeprom programming failed. 0x53 + 0xfe, 0xf0, 0xf1, 0xf2 2 2 enter setups mode and stop sensing, followed by block load of binary setups data from host. command must be repeated 2 times within 100ms or it will fail. returns with 0x53 when ready to accept block. setups 17 0x01 spi mode: flushes pending data from QT1100A. uart mode: serves no function and evokes no response 0..0xff 1 in spi 0 in uart 1 used to get data back in spi mode null 16 0x00 notes return range bytes returned bytes per command description name page hex l q 23 copyright ? 2003-2005 qrg ltd QT1100A-isg r3.02/1105
table 3-2 status commands crc note: where a command returns a crc byte, the crc byte is computed based on the command value itself, plus the data returned (except as noted). crcs are calculated according to the algorithm shown in section 6, page 41. same as 0xc0 (report 1st key), but no crc is appended for faster communications 0..ff 1 (no crc) quick 1st key 21 0xc9 returns the entire setups block, followed by a crc byte; crc is same as ram crc and notably does not include the command itself. setups block data length is 35, + crc makes 36. - 36 (incl. crc) dump setups block 21 0xc8 returns the 1?s complement (inversion) of the last command character received. sending this command two or more times will return its inverse, i.e. 0x38. 0..ff 1 (no crc) return last command 21 0xc7 returns an internal code; a crc byte is appended to the return. 0..ff 2 (incl. crc) internal code 21 0xc6 returns two bytes which indicate all keys in error if any. the first byte returned is the msbyte. key_0 reports in lsbyte bit 0 . 1 = error. a crc byte is appended to the return. 0..03ff 3 (incl. crc) error flags for group 20 0xc5 returns crc of ram setups only; a crc byte is appended to the return. 0..ff 2 (incl. crc) ram crc 20 0xc4 returns crc of eeprom setups only; a crc byte is appended to the return. 0..ff 2 (incl. crc) eeprom crc 20 0xc3 1= calibration error(s) - (non-volatile) 0 1= extreme signals on key(s) - (non-volatile) 4 1= crc error in ram setups (non-volatile) 1 1= reset occurred (non-volatile) 5 1= crc error in eeprom setups (non-volatile) 2 1= eeprom error (non-volatile) 6 1= sync error (non-volatile) 3 1= key(s) detecting (volatile) 7 reports general status of the device. a crc byte is appended to the return. 0..ff 2 (incl. crc) general device status 20 0xc2 returns two bytes which indicate all keys in detection, if any. the first byte returned is the msbyte. key 0 reports in lsbyte bit 0. a crc byte is appended to the return. 0..03ff 3 (incl. crc) report all keys 20 0xc1 key bit_0 0 1= 1 key in detect ; 3 or more keys if both 4 & 5 =1 4 key bit_1 1 1= 2 keys in detect; 3 or more keys if both 4 & 5 =1 5 key bit_2 2 reserved (can report as 0 or 1) 6 key bit_3 3 logical -or of all error types 7 returns byte indicating which key is in detection if any, and also indicates if multiple keys are in detection, and any errors. a crc byte is appended to the return. if no key is in detection, bits 4 & 5 are 0. the first key number is reported in bits 0..3; this lower nibble can have a value from 0..9. the bits in the status byte are: 0..ff 2 (incl. crc) report 1st key 19 0xc0 1= key disabled (by setup or extreme signal - non-volatile) 0 1= detection pending confirmation (volatile) 4 1= extreme signal (non-volatile) 1 unused (0) 5 1= calibration error (non-volatile) 2 unused (0) 6 1= calibration in progress (volatile) 3 1= key in detect (volatile) 7 returns status byte for key k, where k = {0..9} crc byte is appended to the return. the bits in the status byte are: 0..ff 2 (incl. crc) status for key k 19 0x8k returns the detect integrator value for key k, where k = {0..9} the di value is a 4-bit number, 0..0x0f. no crc is appended to the return. diagnostic use only. 0..0f 1 (no crc) di for key k 19 0x6k returns the reference level for key k, where k = {0..9} the reference value is a 16-bit number. no crc is appended to the return. high byte is returned first. diagnostic use only; range is 0..4095. 0..0fff 2 (no crc) ref for key k 19 0x4k returns the raw signal for key k, where k = {0..9} the signal value is a 16-bit number. no crc is appended to the return. high byte is returned first. diagnostic use only; range is 0..4095. 0..0fff 2 (no crc) signal for 1 key 19 0x2k description return range # bytes returned name page code l q 24 copyright ? 2003-2005 qrg ltd QT1100A-isg r3.02/1105
4 setup block functions the setups block controls internal operation including critical functions such as sensitivity, filtering, sample rate, and communications parameters. these functions are summarized in table 4-1, page 31. 4.1 nthr - negative threshold bits bytes 0 - 9, bits 7..4 default value: 9 typical values: see text disabling key(s): 0 see also table 4-2, page 32. the internal signal levels decrease when a key is touched. this phenomenon is related to the charge-transfer acquisition conversion mechanism used by the device. internally the device employs a 16-bit digital reference value for each channel. this reference is determined during the calibration process. after calibration, the reference is either locked or can only move very slowly in response to slow-moving changes in background levels of signal. against this reference, the actual signal can move very fast in response to touch, but when it does so the internal numerical signal value drops below the reference value. the negative threshold (nthr parameter) sets the device sensitivity by controlling the distance that the signal has to travel before creating a detection. each channel has its own nthr setting; these are set in the upper nibbles of setup bytes 0..9. nthr can control the threshold in one of two ways, via the ntm bit contained in byte 32 in the setups block: ntm bit = 0: when ntm is clear, nthr key settings create thresholds based on user-defined offsets from the reference levels. the offsets are based on the setting of nthr, plus 5 counts. thus the available threshold range is from 5 to 20. if nthr is 9, this will create a threshold 14 counts below the key?s reference level. higher numbers mean less sensitivity. this method allows the sensitivity to be altered by changing the value of cs, as well as by changing the value of nthr. this allows a user to conveniently alter key sensitivity without resort to an external eeprom or serial communications; the default key settings of n thr mean that the cs value can be altered proportionately to increase sensitivity. bigger cs = higher gain. ntm bit = 1: when ntm is set, the nthr settings are based on a percentage of the signal reference level. this means that if the reference level doubles, the threshold value also doubles. the reference value is directly related to cs and cx. if cs doubles but n thr is determined as a ratio, the effect is that the device sensitivity does not change at all. due to the physics of the acquisition process, increasing cx will reduce sensitivity even in this mode, just not as much as in the ntm = 0 mode. the nthr value in this mode is set using a percen tage calculation as defined in table 4-2, page 32. if the setting is set very sensitive but the burst length is short (due to a small value of cs and/or large value of cx) then the computed threshold may be too small to process reliably. when this happens the sensitivity is limited internally to a minimum value of 3 counts of signal. disabling of keys: to disable a key, set nthr for that key to 0; this will turn the bursts off for that key but will preserve its timeslot, thus preserving all system timings which depend on the burst spacing. if the system uses the external eeprom or uart or spi communication, the nthr parameter must be used to disable a key. using the sns pins to disable a key will result in an error report. in stand-alone scanport mode with no eeprom present, keys must be disabled using default settings of sns pins as shown on page 4. a key that is legally disabled cannot report an error. see section 2.16, page 14 for more information on error reporting. typical values: for most touch applications where either an eeprom or a serial link is used, use ntm =1 and set nthr = 10 (1.37%) to begin. each key needs to be tailored due to inequalities in stray loading capacitance. for most touch applications where ne ither an eeprom nor a serial link are used, the default setting is 9 + 5 = 14 counts of signal change. key sensitivity can be tailored for each key individually by altering each cs capacitor value. 4.2 nhys - negative hysteresis bits bytes 0 - 9, bits 3..0 default value: 3 typical values: 3, 2 hysteresis controls the level at which the detection process ceases with respect to the threshold level nthr. the hysteresis is controlled by the lower 2 bits of the first 10 bytes of the setups block. the value is expressed as a percentage of the distance measured from the threshold value back up towards the reference. thus given a scenario: signal reference = 732 nthr = 12 counts nhys = 25%, then the signal has to fall to 73 2 - 12 = 720 to cause a detection. the signal has to then rise again to 720 + (12 * 0.25) = 723 for the detection to cease. each key can have its own hysteresis value. generally a low value of hysteresis (12.5%) is enough to solve chatter-type problems. excess hysteresis can cause the sensor to ?stick on? especially if there are underlying problems in wiring or the power supply. typical value: for most touch applications, use 12.5%. 4.3 ndcr / pdcr - drift comp bits ndcr: bytes 10 - 19, bits 7..4 pdcr: byte 31, bits 7..4 default ndcr value: 7 default pdcr value: 5 typical values: tables 4-3 and4-4, pages 32 and 33 signals can drift because of changes in cx and cs over time and temperature. it is crucial that such drift be compensated, or false detections and sensitivity shifts can occur. drift compensation (figure 4-1) is performed by making the reference level track the raw signal at a slow rate, but only while there is no detection in effect. the rate of adjustment must be performed slowly, otherwise legitimate detections l q 25 copyright ? 2003-2005 qrg ltd QT1100A-isg r3.02/1105
could be ignored. the devices drift compensate using a slew-rate limited change to the reference level; the threshold and hysteresis values are slaved to this reference . when a finger is sensed, the signal falls due to the design of the signal conversion process. once a finger is sensed, the drift compensation mechanism ceases since the signal is legitimately detecting an object. drift compensation only works when the signal in question has not crossed the negative threshold level. the drift compensation mechanism can be made asymmetric if desired; the drift -compensation can be made to occur in one direction faster than it does in the other simply by changing the ndcr and pdcr setups parameters. ndcr can be modified on a per-key basis. specifically, drift compensation should be set to compensate faster for increasing signals than for decreasing signals. decreasing signals should not be compensated quickly, since an approaching finger could be compensated for partially or entirely before even touching the touch pad. however, an obstruction over the sense pad, for which the sensor has already made full allowance , could suddenly be removed leaving the sensor with an artificially suppressed reference level and thus become insensitive to touch. in this latter case, the sensor should compensate for the object's removal by raising the reference level relatively quickly. ndcr and pdcr are configured using parameters in the setups block (page 31). the numbers entered for these parameters are used as an entries to lookup tables found on page 32 and page 33 respectively. the actual amount of drift compensation can be read from these tables, which depend on the burst spacing parameter (bs). example: bs = 3.5ms, ndcr = 6; the ndcr rate is 2.15s per lsb change in the reference level when drift compensating negatively (same direction as a touch). example: bs = 2.5ms, pdcr = 9; the pdcr rate is 1.31s per lsb change in the reference level when drift compensating positively (opposing direction to touch). drift compensation and the detection time-outs work together to provide for robust, adaptive sensing. the time-outs provide abrupt changes in reference calibration depending on the duration of the signal 'event'. 4.4 nrd - negative recal delay bits bytes 10 - 19, bits 3..0 default value: 5 typical values: table 4-5, page 34 if a foreign object contacts a key the key's signal may change enough in the negative direction, the same as a normal touch, to create an unintended detection. when this happens it is usually desirable to cause the key to be recalibrated to restore its function after a time delay of some seconds. the negative recal delay timer monitors this detection duration; if a detection event exceeds the timer's setting, the key will be recalibrated. after a recalibration has taken place, the affected key will once again function normally even if it is still being contacted by the foreign object. this feature is set on a per-key basis. it can be disabled if desired by setting this parameter to zero, so that it will not recalibrate automatically (infinite timeout). nrd is configured in the setups block (page 31). the numbers entered for this parameter are used as entries to a lookup table (lut) found on page 34. the actual delay amount can be determined from this table, which depends on the burst spacing parameter (bs). 4.5 prd - positive recal delay bits byte 31, bits 3..0 default value: 7 typical values: table 4-6, page 35 a recalibration can occur automatically if the signal swings more positive than the positive threshold level. this condition can occur if there is positive drift but insufficient positive drift compensation, or if the reference moved negative due to a recalibration, and thereafter the signal returned to normal. as an example of the latter, if a foreign object or a finger contacts a key for a period longer than the negative recal delay (nrd), the key is by recalibrated to a new lower reference level. then, when the condition causing the negative swing ceases to exist (e.g. the object is removed) the signal can suddenly swing back positive to near its normal reference. it is almost always desirable in these cases to cause the key to recalibrate quickly to the new signal level so as to restore normal touch operation. the device accomplishes this by simply setting reference = signal. the time required to detect this condition before recalibrating is governed by prd. for this feature to operate, the signal must rise through the positive threshold level pthr continuously for a period prd. after the prd interval has expired and the recalibration has taken place, the affected key will once again function normally. this interval affects all keys equally. prd is configured in the setups block (page 31). the numbers entered for this parameter are used as entries to a lookup table (lut) found on page 35. the actual delay can be determined from this table, which depends on the burst spacing parameter (bs). 4.6 aks - adjacent key suppression bits bytes 20 - 29, bit 7 default value: 0 (off) the device incorporates adjacent key suppression (?aks? - patent pending) that can be selected on a per-key basis. aks permits the suppression of multiple key presses based on relative signal strength. this feature assists in solving the problem of surface moisture which can bridge a key touch to an adjacent key, causing multiple key presses. this feature is also useful for panels with tightly spaced keys, where a finger might inadvertently activate an adjacent key along with the desired one. l q 26 copyright ? 2003-2005 qrg ltd QT1100A-isg r3.02/1105 figure 4-1 thresholds and drift compensation threshold signal hysteresis reference output
aks works for keys located anywhere and is not restricted to physically adjacent keys; the device has no knowledge of which keys are actually physically adjacent. when enabled for a key, adjacent key suppression causes detections on that key to be suppressed if any other aks-enabled key has a more negative signal deviation from its reference. aks will not function if ndil = 1 for the key. the aks feature requires 2 or more scans of all keys to function, hence ndil must be 2 or greater. 4.7 ek - error key control bits bytes 20 - 29, bit 5 default value: 0 (off) the ek function allows one or more keys to be forced into detection artificially if there is a major error anywhere in the device including on any key. the key to be forced active is selected per-key by the ek bit; any or all 10 keys can be enabled for this function if desired. the reporting of the forced key is via any interface method - scanport, uart, or spi, as well as the led pin if the k2l mode for the chosen key is enabled; note however that major errors force the led pin active regardless of the ek function. the ek function allows error reporting via a redundant path for failure detection purposes, to make key sensing more robust. see also section 3.5.7. 4.8 k2l / ledp / keyo control bits k2l: bytes 20 - 29, bit 4 (one per key) ledp: byte 32, bit 3 keyo: byte 34, bit 7 default k2l value: 0 (off) default ledp value: 0 (active low) default keyo value: 0 (off) the led pin can be used as a health indicator, key detect indicator, and an error status. this pin can act as a backup information source for a host microcontroller to provide for redundant signalling. the led pin is a full push-pull cmos driver. k2l key-to-led function: this bit (one per key) enables the associated key, when active, to force the led pin active for one and only one complete burst cycle (during all 10 keys starting from timeslot 0); this is a one-shot output. if there is also an ongoing major error, the major error takes precedence and led stays solid-active. the 10 s heartbeat pulse (see below) still exists after timeslot 9. it is possible to have multiple keys? k2l bits enabled. k2l can be used to establish a redundant signalling path for important ?halt? or ?panic? keys etc. the keyo function is overridden by k2l for one scan cycle. k2l in standalone mode: k2l is automatically enabled on all keys in standalone mode when no eeprom is present. this can be used to interrupt a host controller whenever any enabled key is touched. heartbeat pulses: at the end of each complete keyscan after the timeslot for key 9, the led pin will pulse low for 10s as a ?health? indicator. the exception to this is if the ledp control bit is high (active high led drive), in which case heartbeat pulses are disabled. it is possible to monitor the heartbeat pulse in a way that confirms the device is operating properly. ledp led polarity function control bit. this bit controls the active polarity of the led output. if it is 0, the led pin is active low (default state). if ledp = 1, the output is active high. in addition, with ledp = 1, heartbeat signals are not present on the led line. keyo key output control bit: this bit causes the led to pulse active if there are keys in detection, during the timeslot of the active key. in addition to the heartbeat pulse after timeslot 9, the led pin will pulse active during the burst of the active key?s timeslot. for example; if key 3 is active, there will be an active keyo pulse during the next occurrence of timeslot 3. the pulse will be as wide as the timeslot. the keyo function is overridden by the k2l function for one scan cycle. the keyo function affects all keys. major errors: any major error (those not involving disabled keys) will cause the led pin to become solid-active. a major error is one where an enabled key signal falls below lbll (section 4.13) or rises above a value of 4095. these conditions can happen if the cs capacitor fails or there is a short in the sns circuit. a major error also includes ram and eeprom crc errors. in standalone mode with no eeprom present, keys are disabled by strapping the sns pins to ?unused? settings (table 1.1 page 4); this will not generate a ?major error? output unless the error occurs after the part has already gone through power-up calibration successfully. the heartbeat ?health? indicator does not appear when a ?major error? condition exists. a ?major error? also overrides the keyo and k2l functions when detected. for more information on error reporting see section 2.16, page 14. 4.9 ndil, fdil - detect integrator bits ndil: bytes 20 - 29, bits 3..0 fdil: byte 32, bits 7..4 default ndil value: 2 default fdil value: 5 typical values: ndil = 2, fdil = 5 to suppress false detections caused by spurious events like electrical noise, the device incorporates a 'detection integrator' or di counter mechanism that acts to confirm a detection by consensus (all detections in sequence must agree). the di mechanism counts sequential detections of a key that appears to be touched, after each burst for the key. for a key to be declared touched, the di mechanism must count to completion without even one detection failure. the di mechanism uses two counters. the first is the ?fast di? counter fdil. when a key?s signal is first noted to be below the negative threshold, the key enters ?fast burst? mode. in this mode the burst is rapidly repeated for up to the specified limit count of the fast di counter. each key has its own counter and its own specified fast-di limit (fdil), which can range from 1 to 15. when fast-burst is entered the device locks onto the key and repeats the acquire burst until the fast-di counter reaches fdil, or, the detection fails beforehand. after this the device resumes normal keyscanning and goes on to the next key. the ?normal di? counter counts the number of times the fast-di counter reached its fdil value. the normal di counter can only increment once per complete scan of all keys. only when the normal di counter reaches ndil does the key become tagged ?active?. the net effect of this is that the sensor can rapidly lock onto and confirm a detection with many confirmations, while still l q 27 copyright ? 2003-2005 qrg ltd QT1100A-isg r3.02/1105
scanning other keys. the ratio of ?fast? to ?normal? counts is completely user-settable via the setups process. the total number of required confirmations is equal to the product of fdil and ndil. example: if fdil = 5 and ndil = 2, the total di count required is 10, even though the device only scanned through all keys twice. the di mechanism is extremely effective at reducing false detections at the expense of slower reaction times. in some applications a slow reaction time is desirable; the di mechanism can be used to intentionally slow down touch response to require the user to touch longer to operate the key. if fdil = 1, the device functions conventionally; each channel acquires only once in rotation , and the normal detect integrator counter (ndil) operates to confirm a detection. the fast-di feature is effectively disabled. if fdil m 2, then the fast-di counter also operates in addition to the ndil counter. if the key has not yet been declared active, the following takes place: 1. if (signal [ nthr): the signal is strong, and the fast-di counter is incremented towards fdil. once fdil is reached, the normal di counter increments once. 2. if (signal > nthr): both the fast-di and normal di counters are cleared due to lack of sufficient signal. 3. if (normal di counter = ndil): the key is declared active. once the key is declared active, the following takes place: 1. if (signal [ nthr): the signal is still strong enough to sustain key detection. the key remains in detection, and the normal di counter increments if it is less than ndil. 2. if (signal > nthr) and (signal [ nhys): the key signal is weak, however the key remains in detection and the normal di counter remains unchanged. 3. if (signal > nhys): there is insufficient signal to sustain key detection, and the n ormal di counter is decremented towards 0. 4. if (normal di counter = 0), the key is declared inactive. 4.10 pthr - positive threshold bits byte 30, bits 7..4 default value: 5 typical value: 4 - 10 the positive threshold is used to provide a mechanism for recalibration of the reference point when a key signal moves abruptly to the positive. this condition is abnormal; it usually occurs after a prolonged touch has caused an automatic recalibration via the nrd parameter, and a subsequent removal of touch causes the signal to rise abruptly above the reference level. the normal desire is to recover from these events quickly , usually in a second or two. pthr is the upper threshold for the detection of these anomalies; phys is the corresponding hysteresis value (see below) used to provide a stable detection criteria. positive recal delay (prd) is the timing function used to time when the key is recalibrated once the positive excursion has been noted. for a further description see phys below. positive drift compensation (pdcr) also works to restore signal levels that are erroneously positive. however this mechanism is much slower and is used primarily to compensate for longer term drift factors, whereas pthr is used to compensate more quickly for fast rises in signal value. the pthr parameter is global to all keys ; it is a single byte parameter common to all. it is measured in counts of signal and can be set from 2..15. 4.11 phys - positive hysteresis bits byte 30, bit 3..0 default value: 1 typical value: 10% of pthr or 1 count (whichever is greater) positive hysteresis is used in setting the drop out level at which a positive detection ceases (see pthr above). the value is expressed as a signal count from the positive threshold value back down towards the reference. thus given a scenario: reference = 732 pthr = 5 counts phys = 1, then the signal has to rise to 73 2 + 5 = 737 to cause a positive detection. at this point the positive recal delay (prd) engages and starts timing the signal excursion. providing that the signal level does not fall below 736 (1 count of hysteresis below 737) the timer will continue until it expires, at which point the affected key is fully recalibrated (and only that key). the phys parameter is global to all keys ; it is a single byte parameter common to all. it is measured in counts of signal and can be set from 0..15. 4.12 se, sync control bits byte 32, bits 1, 0 default se value: 0 (off) default sync value: 0 (level sensing) the sync functions allow the device to synchronize to external clock sources or to other similar devices to prevent interference effects. most interference in capacitance sensors comes from beat frequency and alias generation due to non-coherency between the sampling rate of the sensor and an external noise source. another similar sensor can be considered a noise source. the QT1100A offers two ways to limit this kind of interference: 1. level sensing: make sure the QT1100A does not sample at the same time as a similar device, where physically adjacent keys are concerned. 2. edge sensing: synchronize the QT1100A to an external repetitive noise source so that there are no beat frequencies generated and the interference shows up as a benign dc offset to the acquired signal. the se (?sync enable?) bit determines whether or not sync is used. sync can be enabled by setting se = 1. if se = 0, the part runs asynchronously regardless of the state of the sync pin. the sync bit determines which mode, 1 or 2, the device operates in if se = 1. l q 28 copyright ? 2003-2005 qrg ltd QT1100A-isg r3.02/1105
se in standalone mode: se is automatically enabled (= 1) in standalone mode when no eeprom is present. sync mode: if sync = 0, the device uses the sync pin to communicate to another similar part (e.g. one or more additional QT1100A?s). QT1100A?s connected together in this way will self- synchronize so that they all acquire on key 0 at the same time. provided that the devices run at a similar clock rate and have the same burst spacing (bs) parameters the devices will remain locked over their full acquisition cycles, key for key. in this condition it is easy to design a pcb where keys from multiple QT1100A?s are physically adjacent but not of the same key number; thus ensuring that adjacent keys are never acquiring at the same time and cannot interfere with each other. level mode: if sync = 0, the device operates in a level sensing mode. the open-drain sync pin is pulled low by each device that is currently sensing on any key but key 0. after the last key is sensed (key 9) the device floats the sync pin and then waits until the sync pin actually floats high. any other devices sharing the sync pin will also clamp the sync pin low until they are done sensing all their keys. finally when all devices are waiting to start acquiring on key 0, the sync line will actually float high, and the sensor devices will then all acquire key 0 in unison. edge mode: if sync = 1, the part waits for a positive edge on the sync pin to begin acquiring on key 0. thereafter the other keys also acquire in sequence according to the bs setup. sync = 1 should be used for external noise source or power line synchronization. a simple rc circuit can be connected from a mains supply to the sync pin to ensure phase- aligned triggering. sync can operate from 10hz ~ 400hz. if se = 1 in uart mode, holding pin rx = 0 for excessive periods, or in spi mode, holding pin /ss = 0, will prevent proper operation of sync. since communication has higher priority than sync, communicating during a sync active edge will cause an additional delay of the sync process and result in timing skews. holding either /ss or rx low continuously will inhibit sync. these control bits apply to the device as a whole. 4.13 lbll - lower burst length limit byte 33 default value: 3 typical value: 50 - 100 lbll is an fmea-oriented limits feature used to detect keys that are not operating properly. if a key is short circuited, or its cs/rs sensing circuit has failed, the acquired signal will be either one count or attempt to be infinite. lower errors are caught using the lbll parameter which can be set from 0 to 255. if {signal < lbll}, the key is flagged as having an error and the acquisition burst for that key is also disabled until the part is reset or the key is recalibrated. setting lbll = 0 will disable this error detection feature and also stop the ability of a key to be self-disabled if there is a serious hardware error. a better method for disabling the lbll feature is to set it to a very low value such as 3. this way the device can still stop acquiring on channels that have serious hardware problems, yet not generate errors when signals are merely very low. if lbll is set too high, it could cause legitimate touch detections to trigger an error flag and self-disable a channel. upper errors are caught using a built-in, fixed upper burst length limit of 4095; beyond this value of signal, the key is tagged as being in error. 4.14 bs - burst spacing control bits byte 34, bits 4,3,2 default value: 2 (3ms) typical values: 1 - 4 the interval of time from the start of a burst on one key to the start of the burst on the next key is known as the burst spacing . this is an alterable parameter which affects all keys. the burst spacing can be viewed as a timeslot in which an acquisition burst occurs. this approach results in an orderly and predictable sequencing of key scanning with predictable response times. shorter spacings result in a faster response time to touch; longer spacings permit higher burst lengths and longer conversion times but slow down response time. standard bs settings from 2ms to 7ms are available. bs should be set so that the acquire burst lengths themselves are fully contained in their timeslots, plus 500s left over. this can be determined by using a 10x scope probe with a 470k resistor in series and examining the length of the distorted waveform (this is done to minimize loading effects which reduce the burst length). if an acquisition burst exceeds its timeslot, the device will still operate properly except that time based parameters will be increased in duration; the timeslots will expand to fill the burst length which is always variable. the bs value is obtained via a lookup table (lut) : 4.15 br - baud rate control bits byte 34, bits 1, 0 default value: 1 (9600) the br setting allows control over the baud rate, from 4800 to 28.8k baud according to the following table: if the baud rate is altered via serial communications, the new baud rate is effective immediately after the setup block loads are complete, that is, after the QT1100A sends the final response from the load setup command (0x01). l q 29 copyright ? 2003-2005 qrg ltd QT1100A-isg r3.02/1105 7.0ms 7 6.0ms 6 5.0ms 5 4.0ms 4 3.5ms 3 3.0ms 2 2.5ms 1 2.0ms 0 setting bs value 28,800 3 19,200 2 9,600 1 4,800 0 setting br value
4.16 hcrc - host crc byte 35 hcrc is an 8-bit crc code calculated according to ccitt-8 (see page 41) appended to the end of the setups table. this code must be sent with each serial transmission of the setups block. an error in the crc will manifest itself as an error code , and if this occurs, factory default parameters will be automatically loaded to provide a ?safe?, defined recovery . the crc can also be replaced with a 0xd6 which will inhibit crc checking. care should be taken so that the crc is never actually 0xd6 (if crc checking is desired). this can be done by altering any unused setup parameter. l q 30 copyright ? 2003-2005 qrg ltd QT1100A-isg r3.02/1105
table 4-1 serial / eeprom setups block data can be sent from the host to the QT1100A in a block of hex data over a serial port. a setups block received via serial tra nsmission is loaded into ram (and also into eeprom if one is connected). setups mode is initiated by sending two sequential 0x01 commands to the device. if each byte in the block load sequence is not within 100ms of the preceding byte, the command will fail and default values or eeprom values will be used instead of the received setups block. eeprom setups are a copy of ram setups except that eeprom location 0 will contain 0xd6. location 0 of the eeprom must contain 0 xd6 or it will not be read. the setups block can also be preloaded into eeprom to control stand-alone (scanport) mode. if the initial 0xd6 is read at power-up, the re mainder of the eeprom is then loaded (provided the eeprom crc is acceptable). eeprom address location 1 corresponds to setups block byte 0. if the last eeprom byte is also fi xed at 0xd6 in place of a crc, eeprom crc checking is disabled. note: after any setups changes, the part should be recalibrated using 0x03 (enter cal mode). data area is 35 bytes; plus crc makes 36. eeprom area has 37 bytes which also includes an initial 0xd6 byte. 36 - block length 30 crc of above setups block (0xd6 disables crc checking). see page 41 for algorithm. device 8 1 hcrc host crc 0x23 35 27 - 29 - 29 bit_7 = led pin also shows keypress if keyo = 1 bit_6,5 = unused bit_4,3,2 = burst spacing (bs), 8 values in increasing order - 2ms, 2.5ms, 3ms, 3.5ms, 4ms, 5ms, 6ms, 7ms settings bit_1,0 = baud rate (br); 4 values; uart mode only 4800, 9600 (default), 19.2k, 28.8k in increasing order 0 (disable) 3 (binary ?11?) 2 (3ms) 1 (9600) device - device device 1 2 3 2 0, 1 - 0..7 0..3 1 keyo unused bs br control bits 0x22 34 29 lower limit of acceptable burst length; below this, declares error. default = 3 (error on catastrophic channel failure) 0x03 10 8 0..255 1 lbll lower bl limit 0x21 33 27 27 25 28 - 28 upper nibble = fast neg di limit; min = 1 bit_3: 1 = led pin is inverted bit_2: 1 = ratiometric neg thesh; 0 = fixed thresholds. bit_1: 1 = sync enabled (default = 0, disabled) note: in standalone mode with no eeprom, sync = 1 (enabled) bit_0: sync mode (default = 0, level; 1 = edge) 5 0 (normal) 0 (fixed) 0 (off)* 0 (level) 10 device 10 device device 4 1 1 1 1 1..15 0, 1 0, 1 0, 1 0, 1 1 fdil ledp ntm se sync fast (neg) di limit led polarity neg thresh mode sync enable sync pin mode 0x20 32 25 26 upper nibble = pdcr; 0 = no pdc; (via lut, page 33) lower nibble = prd; (via lut, page 35) 5 (0.68s @3ms) 7 (1.03s @3ms) 10 10 4 4 0..15 0..15 1 pdcr prd pos drift comp rate pos recal delay 0x1f 31 28 28 upper nibble = pos threshold; sets sensitivity to +recal lower nibble = pos hysteresis, counts down from +thresh 5 1 10 10 4 4 2..15 0..15 1 pthr phys pos thresh pos hyst 0x1e 30 26 - 27 27 - 27 bit_7: 1 = aks enable (each key) bit_6: unused bit_5: ek - key forced active on major error (each key) bit_4: 1 = key to led function enable (each key) note: in standalone mode with no eeprom, k2l = 1 (enabled) on all keys lower nibble = norm di limit; thresh crossings to detection; min = 1 0 (disable) 0 0 (off) 0 (off)* 2 1 - 1 1 1 1 1 1 1 4 0, 1 - 0, 1 0, 1 1..15 10 aks unused ek k2l ndil aks enable unused error key key to led normal det int limit 0x14..0x1d 20..29 25 26 upper nibble = ndcr; 0 = no ndc (via lut, page 32) lower nibble = nrd; 0 = infinite (via lut, page 34) 7 (2.18s @3ms) 5 (14.42s @3ms) 1 1 4 4 0..15 0..15 10 ndcr nrd neg drift comp rate neg recal delay 0x0a..0x13 10..19 25 - 25 upper nibble = neg threshold; 0 = key disabled bit_3, 2: unused lower nibble = neg hysteresis, 3 = 12.5%, 2 = 25%, 1 = 50%, 0 = 0% 9 0 3 1 - 1 4 2 2 0..15 - 0..3 10 nthr unused nhys neg thresh unused neg hyst 0x00..0x09 0..9 page description default value key scope bits valid range byte len sym parameter block byte # l q 31 copyright ? 2003-2005 qrg ltd QT1100A-isg r3.02/1105
table 4-2 nthr ratiometric threshold values this section assumes bit ntm = 1 (in byte 32 - see table 4-1). threshold values established by the nthr setup are made in terms of signal deviation expressed as a percentage of the reference value. this gives key sensitivity a great tolerance towards part variances, deviations in cs , and to a good ex tent, cx. settings are subject to a minimum of 3 counts of signal, which can come into play with short burst lengths and low percentages. the values are as follows: 0.39% 0.59% 0.78% 0.98% 1.17% 1.37% 1.56% 1.95% 2.34% 2.73% 3.13% 3.91% 4.69% 5.47% 6.25% disabled ? ? ? ? percentage of reference less sensitive more sensitive - sensitivity 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 setup value if ntm = 0, the threshold is based on the raw numerical value entered for each channel in the nthr parameter in setup bytes 0.. 9 plus 5 co unts, and can thus range from 5 to 20 (0 + 5... 15 + 5). ntm = 0 (the default setting) is useful in standalone applications, where key gains are adjusted by changing the value of cs or cx for each key. 4.17 timing tables lookup tables (luts) translate several setups values into actual internal parameters. ndcr example: bs = 4ms, ndcr = 6. the act ual ndcr is then 2.46s per adjustment. table 4-3 ndcr negative drift compensation rate lookup table (lut) -127 26.78 22.95 19.13 15.30 13.39 11.48 9.56 7.65 15 -103 21.74 18.63 15.53 12.42 10.87 9.31 7.76 6.21 14 -84 17.75 15.21 12.68 10.14 8.87 7.60 6.34 5.07 13 -68 14.39 12.33 10.28 8.22 7.19 6.16 5.14 4.11 12 -55 11.66 9.99 8.32 6.66 5.83 4.99 4.16 3.33 11 -45 9.55 8.19 6.82 5.46 4.78 4.10 3.41 2.73 10 -37 7.87 6.75 5.62 4.50 3.94 3.38 2.81 2.25 9 -30 6.40 5.49 4.58 3.66 3.20 2.75 2.29 1.83 8 -24 5.14 4.41 3.68 2.94 2.57 2.21 1.84 1.47 7 -20 4.31 3.69 3.08 2.46 2.15 1.85 1.54 1.23 6 -16 3.47 2.97 2.48 1.98 1.73 1.49 1.24 0.99 5 -13 2.84 2.43 2.03 1.62 1.42 1.22 1.01 0.81 4 -11 2.42 2.07 1.73 1.38 1.21 1.04 0.86 0.69 3 -9 2.00 1.71 1.43 1.14 1.00 0.85 0.71 0.57 2 -7 1.58 1.35 1.13 0.90 0.79 0.67 0.56 0.45 1 0 disabled disabled disabled disabled disabled disabled disabled disabled 0 bs = 7ms bs = 6ms bs = 5ms bs = 4ms bs = 3.5ms bs = 3ms bs = 2.5ms bs = 2ms 1.23 lut value ndcr time, seconds setups value gray numbers are preferred values for most touch control applications l q 32 copyright ? 2003-2005 qrg ltd QT1100A-isg r3.02/1105
table 4-4 pdcr positive drift compensation lookup table (lut) 60 12.71 10.89 9.07 7.26 6.35 5.44 4.54 3.60 15 49 10.40 8.91 7.42 5.94 5.20 4.46 3.71 2.97 14 40 8.50 7.29 6.07 4.86 4.25 3.65 3.04 2.43 13 32 6.82 5.85 4.87 3.90 3.41 2.93 2.44 1.95 12 26 5.56 4.77 3.98 3.18 2.78 2.39 1.99 1.59 11 21 4.52 3.87 3.23 2.58 2.26 1.94 1.61 1.29 10 17 3.68 3.15 2.63 2.10 1.84 1.58 1.31 1.05 9 14 3.05 2.61 2.18 1.74 1.52 1.31 1.09 0.87 8 11 2.42 2.07 1.73 1.38 1.21 1.04 0.86 0.69 7 9 2.00 1.71 1.43 1.14 1.00 0.85 0.71 0.57 6 8 1.79 1.53 1.28 1.02 0.89 0.76 0.64 0.51 5 6 1.37 1.17 0.97 0.78 0.68 0.58 0.49 0.39 4 5 1.16 0.99 0.82 0.66 0.58 0.50 0.41 0.33 3 4 0.94 0.81 0.67 0.54 0.47 0.41 0.34 0.27 2 3 0.73 0.63 0.52 0.42 0.37 0.32 0.26 0.21 1 0 disabled disabled disabled disabled disabled disabled disabled disabled 0 bs = 7ms bs = 6ms bs = 5ms bs = 4ms bs = 3.5ms bs = 3ms bs = 2.5ms bs = 2ms 1.23 lut value pdcr time, seconds setups value gray numbers are preferred values for most touch control applications l q 33 copyright ? 2003-2005 qrg ltd QT1100A-isg r3.02/1105
table 4-5 nrd negative recal delay lookup table (lut) -127 267.8 229.5 191.3 153.0 133.9 114.8 95.6 76.5 15 -103 217.3 186.3 155.3 124.2 108.7 93.2 77.6 62.1 14 -84 177.4 152.1 126.8 101.4 88.7 76.0 63.4 50.7 13 -68 143.8 123.3 102.8 82.2 71.9 61.6 51.4 41.1 12 -55 116.6 99.9 83.3 66.6 58.3 50.0 41.6 33.3 11 -45 95.5 81.9 68.3 54.6 47.8 41.0 34.1 27.3 10 -37 78.8 67.5 56.3 45.0 39.4 33.8 28.1 22.5 9 -30 64.0 54.9 45.8 36.6 32.0 27.4 22.9 18.3 8 -24 51.5 44.1 36.8 29.4 25.7 22.1 18.4 14.7 7 -20 43.0 36.9 30.8 24.6 21.5 18.4 15.4 12.3 6 -16 34.6 29.7 24.8 19.8 17.3 14.9 12.4 9.9 5 -13 28.4 24.3 20.3 16.2 14.2 12.2 10.1 8.1 4 -11 24.1 20.7 17.3 13.8 12.1 10.4 8.6 6.9 3 -9 19.9 17.1 14.3 11.4 10.0 8.6 7.1 5.7 2 -7 15.8 13.5 11.3 9.0 7.9 6.8 5.6 4.5 1 0 infinite infinite infinite infinite infinite infinite infinite infinite 0 bs = 7ms bs = 6ms bs = 5ms bs = 4ms bs = 3.5ms bs = 3ms bs = 2.5ms bs = 2ms 1.23 lut value nrd time, seconds setups value gray numbers are preferred values for most touch control applications l q 34 copyright ? 2003-2005 qrg ltd QT1100A-isg r3.02/1105
table 4-6 prd positive recal delay lookup table (lut) 60 12.71 10.89 9.07 7.26 6.35 5.44 4.54 3.63 15 49 10.40 8.91 7.42 5.94 5.20 4.46 3.71 2.97 14 40 8.50 7.29 6.07 4.86 4.25 3.65 3.04 2.43 13 32 6.82 5.85 4.87 3.90 3.41 2.93 2.44 1.95 12 26 5.56 4.77 3.98 3.18 2.78 2.39 1.99 1.59 11 21 4.52 3.87 3.23 2.58 2.26 1.94 1.61 1.29 10 17 3.68 3.15 2.63 2.10 1.84 1.58 1.31 1.05 9 14 3.05 2.61 2.18 1.74 1.52 1.31 1.09 0.87 8 11 2.42 2.07 1.73 1.38 1.21 1.04 0.86 0.69 7 9 2.00 1.71 1.43 1.14 1.00 0.85 0.71 0.57 6 8 1.79 1.53 1.28 1.02 0.89 0.76 0.64 0.51 5 6 1.37 1.17 0.97 0.78 0.68 0.58 0.49 0.39 4 5 1.16 0.99 0.82 0.66 0.58 0.50 0.41 0.33 3 4 0.94 0.81 0.67 0.54 0.47 0.41 0.34 0.27 2 3 0.73 0.63 0.52 0.42 0.37 0.32 0.26 0.21 1 0 infinite infinite infinite infinite infinite infinite infinite infinite 0 bs = 7ms bs = 6ms bs = 5ms bs = 4ms bs = 3.5ms bs = 3ms bs = 2.5ms bs = 2ms 1.23 lut value prd time, seconds setups value gray numbers are preferred values for most touch control applications l q 35 copyright ? 2003-2005 qrg ltd QT1100A-isg r3.02/1105
5 - specifications 5.1 absolute maximum specifications operating temp,ta ........................................................................................ -40 ~ +85c storage temp ........................................................................................... -50 ~ +125c vdd.................................................................................................... -0.3 ~ +5.5v max continuous pin current, any control or drive pin .............................................................. 20ma short circuit duration to ground, any pin ......................................................................... infinite short circuit duration to vdd, any pin ............................................................................ infinite voltage forced onto any pin ................................................................... -0.3v to (vdd + 0.3) volts 5.2 recommended operating conditions v dd .................................................................................................... +3.3 ~ +5.0v fosc (resonator) .............................................................................................. 12mhz short-term supply ripple+noise ................................................................................ 5mv/s long-term supply stability .................................................................................... 100mv cs value ............................................................................................... 1nf to 100nf cx value ..................................................................................................0 to 100pf 5.3 ac specifications vdd = 5.0v, ta = recommended, cx = 5pf, cs = 22nf, fosc = 12mhz ms 700 max allowable sleep time tsm bs = 3ms, di = 3, fdi = 1 ms 90 response time tr spread spectrum range khz 235 175 burst frequency range fqt counts 500 burst length, each channel nbl burst spacing = 3ms ms 30 acquisition time, all channels tac s 2 charge-transfer duration tpc s 120 scanport latency tsl from sleep mode s 160 150 comms start-up time from wake tws tsu+trc comms start-up time from reset tcs burst spacing = 3ms; changes proportionately at other spacings ms 500 450 recalibration time trc does not include recalibration time ms 400 start-up time from cold start tsu resonator frequency mhz 14 12 6 oscillator range fosc notes units max typ min description parameter 5.4 dc specifications vdd = 5.0v, cs = 22nf, cx = 5pf, fosc = 12mhz; ta = recommended range, unless noted bits 9 acquisition resolution a r a 1 input leakage current i il 2.5ma source v vdd-0.5 high output voltage v oh 7ma sink v 0.5 low output voltage v ol v 3.5 high input logic level v hl v 0.7 low input logic level v il req?d for start-up, w/o external reset ckt v/s 100 supply turn-on slope v dds @ vdd = 5.0 @ vdd = 3.3 a 20 10 supply current, sleep mode i dds @ vdd = 5.0 @ vdd = 4.0 @ vdd = 3.6 @ vdd = 3.3 ma 5 2.9 2 1.7 1.4 supply current, run mode i ddr notes units max typ min description parameter l q 36 copyright ? 2003-2005 qrg ltd QT1100A-isg r3.02/1105
5.5 burst / sync timing see section 5.7 for timing parameters l q 37 copyright ? 2003-2005 qrg ltd QT1100A-isg r3.02/1105 twbl floats high mode 0 (level sensing) sync shown sync key 0 burst burst_key0 key 1 burst burst_key1 t3 crd y twbs twcrdy
5.6 spi timing diagram see section 5.7 for timing parameters 1. host first waits for QT1100A to float crdy high (using pull-up resistor) 2. host asserts /ss line low 3. host shifts out byte to QT1100A using 8 falling edges of clk, on QT1100A pin di 4. QT1100A shifts data out back to host on the same falling edges of clk, on QT1100A pin do 5. QT1100A and host both shift data in on the rising edges of clk 6. host releases /ss high 7. crdy may be pulled low again by QT1100A at any time after /ss is pulled low 8. host must send nulls to shift out expected return data l q 38 copyright ? 2003-2005 qrg ltd QT1100A-isg r3.02/1105 twcrdy pulled (floats) high crdy from qt clamped low by qt t5 /ss from host data shifts out on falling edge clk from host host data output (slave input - di) qt data output 3-state 3-state (slave out - do) data shifts in on rising edge of sck 0 ?7 ?7 10 76543210 4321 ? 765 5432 076 ? 65 ? 65 4321 ?765 t7 tcyc t8 t6 t9 t4
5.7 QT1100A timing parameters - with fosc = 12mhz note 1: twcrdy can last from the end of a burst until the completion of the inter-burst dead-time, i .e. just before the next channel?s burst. note 2: burst spacing will be expanded if the burst time + burst processing time is longer. note 3: this setting is determined by setups, or defaults to 3ms note 4: min time that di pin must be valid prior to clk going high note 5: 100khz max clock rate l q 39 copyright ? 2003-2005 qrg ltd QT1100A-isg r3.02/1105 5 s 1,000 10 clk period tcyc s 4 2 delay time, clk to do t9 s 2 hold time, clk to di t8 4 s 2 setup time, di to clk t7 ms twbs /ss high min recovery time t6 s 100 10 /ss to clk duration t5 s 10 crdy to /ss max delay (grace period) t4 s 100 50 burst to crdy delay t3 2, 3 ms 10 2 burst spacing time twbs ms 2.5 acquisition burst length twbl 1 s twbs - twbl 240 crdy high (ready to communicate) twcrdy notes units max typ min description parameter
5.8 current vs vdd fosc = 12mhz, ta = 20oc, cs = 22nf, cx = 5pf typ idd vs. vdd 5.9 mechanical all dimensions in thousandths of an inch (imperial mils) 5.10 marking l q 40 copyright ? 2003-2005 qrg ltd QT1100A-isg r3.02/1105 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 3.0 3.5 4.0 4.5 5.0 5.5 vdd (v) current (ma ) yes QT1100A-isg 10 QT1100A-isg -40oc to +85oc lead-free marking keys ssop part number t a
6 appendix a - 8-bit crc c algorithm // 8-bit crc calculation. initial value is 0. // polynomial = x 8 + x 5 + x 4 + 1 // data is an 8 bit number; crc is an 8-bit number int eight_bit_crc(int crc, int data) { int index; // shift counter int fb; index = 8; // initialise the shift counter do { fb = (crc ^ data) & 0x01; data >>= 1; crc >>= 1; if(fb) { crc ^= 0x8c; } } while(--index); return crc; } a crc calculator for windows is available free of charge from quantum research. l q 41 copyright ? 2003-2005 qrg ltd QT1100A-isg r3.02/1105
l q copyright ? 2001-2005 qrg ltd. all rights reserved patented and patents pending worldwide corporate headquarters 1 mitchell point ensign way, hamble so31 4rf great britain tel: +44 (0)23 8056 5600 fax: +44 (0)23 80565600 www.qprox.com north america 651 holiday drive bldg. 5 / 300 pittsburgh, pa 15220 usa tel: 412-391-7367 fax: 412-291-1015 this device covered under one or more of the following united states and international patents: 5,730,165, 6,288,707, 6,377,009 , 6,452,514, 6,457,355, 6,466,036, 6,535,200. numerous further patents are pending which may apply to this device or the applicat ions thereof. the specifications set out in this document are subject to change without notice. all products sold and services supplied by qr g are subject to our terms and conditions of sale and supply of services which are available online at www.qprox.com and are supplied with every order acknowledgement. qprox, qtouch, qmatrix, qlevel, and qslide are trademarks of qrg. qrg products are not suitable fo r medical (including lifesaving equipment), safety or mission critical applications or other similar purposes. except as expressl y set out in qrg's terms and conditions, no licenses to patents or other intellectual property of qrg (express or implied) are granted by qr g in connection with the sale of qrg products or provision of qrg services. qrg will not be liable for customer product design and customers are entirely responsible for their products and applications which incorporate qrg's products.

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